maichong.vhd

来自「在quartus开发环境下」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity maichong is
port(clk:in std_logic;-----时钟
     clr:in std_logic;-----清零
     q0,q1,q2:out std_logic);----脉冲输出
end;
architecture one of maichong is
	signal y,x:std_logic_vector(2 downto 0);
begin
process(clk,clr)
begin
if clk'event and clk='1' then
	if clr='1' then 
	   y<="000";x<="001";
	else
	   y<=x;
	   x<=x(1 downto 0)&x(2);----循环移位
	end if;
end if;
end process;
	q0<=y(0);
	q1<=y(1);
	q2<=y(2);
end;