anyodd_div1.vhd

在quartus开发环境下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity anyodd_div1 is
generic(n:integer:=5);----设置分频系数
port(clk:in std_logic;-------时钟
     clkdiv:buffer std_logic);----输出分频信号
end;
architecture one of anyodd_div1 is
	signal cnt1:integer:=0;---计数器1
	signal cnt2:integer:=0;---计数器2
	signal clk_temp:std_logic;----脉冲控制端
begin
--------------------上升沿触发计数器进程
process(clk)
begin
if clk'event and clk='1' then
	if cnt1=n-1 then
	cnt1<=0;
	else cnt1<=cnt1+1;
	end if;
end if;
end process;
---------------------下降沿触发计数器进程
process(clk)
begin
if clk'event and clk='0' then
	if cnt2=n-1 then
	cnt2<=0;
	else cnt2<=cnt2+1;
	end if;
end if;
end process;
-----------------------对两个计数器的计数进行控制
process(cnt1,cnt2)
begin
    if cnt1=1 then
		if cnt2=0 then
		clk_temp<='1';
		else clk_temp<='0';
		end if;
	elsif cnt1=(n+1)/2 then
		if cnt2=(n+1)/2 then
		clk_temp<='1';
		else clk_temp<='0';
		end if;
	else 
	clk_temp<='0';
	end if;
end process;
-------------------------利用脉冲控制端的上升沿来控制分频信号的输出
process(clk_temp,clk)
begin
if clk_temp'event and clk_temp='1' then
	clkdiv<=not clkdiv;
end if;
end process;
end;