shop.fit.qmsg

来自「在quartus开发环境下」· QMSG 代码 · 共 37 行 · 第 1/3 页

{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.304 ns register register " "Info: Estimated most critical path is register to register delay of 7.304 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns item\[0\] 1 REG LAB_X13_Y9 120 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y9; Fanout = 120; REG Node = 'item\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { item[0] } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.621 ns) 2.621 ns ram\[1\]\[2\]~7127 2 COMB LOOP LAB_X14_Y9 2 " "Info: 2: + IC(0.000 ns) + CELL(2.621 ns) = 2.621 ns; Loc. = LAB_X14_Y9; Fanout = 2; COMB LOOP Node = 'ram\[1\]\[2\]~7127'" { { "Info" "ITDB_PART_OF_SCC" "ram\[1\]\[2\]~7127 LAB_X14_Y9 " "Info: Loc. = LAB_X14_Y9; Node \"ram\[1\]\[2\]~7127\"" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram[1][2]~7127 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "ram~7126 LAB_X14_Y9 " "Info: Loc. = LAB_X14_Y9; Node \"ram~7126\"" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram~7126 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram[1][2]~7127 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram~7126 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 21 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.621 ns" { item[0] ram[1][2]~7127 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.902 ns) + CELL(0.624 ns) 4.147 ns qua~210 3 COMB LAB_X14_Y8 1 " "Info: 3: + IC(0.902 ns) + CELL(0.624 ns) = 4.147 ns; Loc. = LAB_X14_Y8; Fanout = 1; COMB Node = 'qua~210'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { ram[1][2]~7127 qua~210 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.167 ns) + CELL(0.366 ns) 5.680 ns qua~211 4 COMB LAB_X14_Y6 1 " "Info: 4: + IC(1.167 ns) + CELL(0.366 ns) = 5.680 ns; Loc. = LAB_X14_Y6; Fanout = 1; COMB Node = 'qua~211'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.533 ns" { qua~210 qua~211 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.865 ns) + CELL(0.651 ns) 7.196 ns qua\[2\]~143 5 COMB LAB_X18_Y6 1 " "Info: 5: + IC(0.865 ns) + CELL(0.651 ns) = 7.196 ns; Loc. = LAB_X18_Y6; Fanout = 1; COMB Node = 'qua\[2\]~143'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.516 ns" { qua~211 qua[2]~143 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.304 ns qua\[2\] 6 REG LAB_X18_Y6 15 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 7.304 ns; Loc. = LAB_X18_Y6; Fanout = 15; REG Node = 'qua\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { qua[2]~143 qua[2] } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.370 ns ( 59.83 % ) " "Info: Total cell delay = 4.370 ns ( 59.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.934 ns ( 40.17 % ) " "Info: Total interconnect delay = 2.934 ns ( 40.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.304 ns" { item[0] ram[1][2]~7127 qua~210 qua~211 qua[2]~143 qua[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}