lpm_fifo.map.rpt

来自「在quartus开发环境下」· RPT 代码 · 共 326 行 · 第 1/3 页

; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 6     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram ;
+---------------------------------+--------------------+------+------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                               ;
+---------------------------------+--------------------+------+------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                ;
+---------------------------------+--------------------+------+------------------------------------------------------------------+


+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: fifo:inst|scfifo:scfifo_component ;
+-------------------------+------------+-----------------------------------------+
; Parameter Name          ; Value      ; Type                                    ;
+-------------------------+------------+-----------------------------------------+
; AUTO_CARRY_CHAINS       ; ON         ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS    ; OFF        ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS     ; ON         ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS  ; OFF        ; IGNORE_CASCADE                          ;
; lpm_width               ; 8          ; Signed Integer                          ;
; LPM_NUMWORDS            ; 32         ; Signed Integer                          ;
; LPM_WIDTHU              ; 5          ; Signed Integer                          ;
; LPM_SHOWAHEAD           ; OFF        ; Untyped                                 ;
; UNDERFLOW_CHECKING      ; ON         ; Untyped                                 ;
; OVERFLOW_CHECKING       ; ON         ; Untyped                                 ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF        ; Untyped                                 ;
; ADD_RAM_OUTPUT_REGISTER ; ON         ; Untyped                                 ;
; ALMOST_FULL_VALUE       ; 0          ; Untyped                                 ;
; ALMOST_EMPTY_VALUE      ; 0          ; Untyped                                 ;
; USE_EAB                 ; ON         ; Untyped                                 ;
; MAXIMIZE_SPEED          ; 5          ; Untyped                                 ;
; DEVICE_FAMILY           ; Stratix    ; Untyped                                 ;
; OPTIMIZE_FOR_SPEED      ; 5          ; Untyped                                 ;
; CBXI_PARAMETER          ; scfifo_0mv ; Untyped                                 ;
+-------------------------+------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                   ;
+----------------------------+-----------------------------------+
; Name                       ; Value                             ;
+----------------------------+-----------------------------------+
; Number of entity instances ; 1                                 ;
; Entity Instance            ; fifo:inst|scfifo:scfifo_component ;
;     -- FIFO Type           ; Single Clock                      ;
;     -- lpm_width           ; 8                                 ;
;     -- LPM_NUMWORDS        ; 32                                ;
;     -- LPM_SHOWAHEAD       ; OFF                               ;
;     -- USE_EAB             ; ON                                ;
+----------------------------+-----------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Mon Apr 23 16:19:08 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lpm_fifo -c lpm_fifo
Warning: Entity "lpm_fifo" obtained from "D:/my_eda2/lpm_fifo/lpm_fifo.bdf" instead of from Quartus II megafunction library
Info: Found 1 design units, including 1 entities, in source file lpm_fifo.bdf
    Info: Found entity 1: lpm_fifo
Info: Elaborating entity "lpm_fifo" for the top level hierarchy
Warning: Using design file fifo.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: fifo-SYN
    Info: Found entity 1: fifo
Info: Elaborating entity "fifo" for hierarchy "fifo:inst"
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus ii7.0/quartus/libraries/megafunctions/scfifo.tdf
    Info: Found entity 1: scfifo
Info: Elaborating entity "scfifo" for hierarchy "fifo:inst|scfifo:scfifo_component"
Info: Elaborated megafunction instantiation "fifo:inst|scfifo:scfifo_component"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_0mv.tdf
    Info: Found entity 1: scfifo_0mv
Info: Elaborating entity "scfifo_0mv" for hierarchy "fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_7sv.tdf
    Info: Found entity 1: a_dpfifo_7sv
Info: Elaborating entity "a_dpfifo_7sv" for hierarchy "fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qla1.tdf
    Info: Found entity 1: altsyncram_qla1
Info: Elaborating entity "altsyncram_qla1" for hierarchy "fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/cntr_rua.tdf
    Info: Found entity 1: cntr_rua
Info: Elaborating entity "cntr_rua" for hierarchy "fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb"
Info: Found 1 design units, including 1 entities, in source file db/cntr_8v6.tdf
    Info: Found entity 1: cntr_8v6
Info: Elaborating entity "cntr_8v6" for hierarchy "fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter"
Info: Found 1 design units, including 1 entities, in source file db/cntr_sua.tdf
    Info: Found entity 1: cntr_sua
Info: Elaborating entity "cntr_sua" for hierarchy "fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_sua:wr_ptr"
Info: Implemented 75 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 15 output pins
    Info: Implemented 41 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 148 megabytes of memory during processing
    Info: Processing ended: Mon Apr 23 16:19:19 2007
    Info: Elapsed time: 00:00:11