lpm_fifo.sim.rpt

来自「在quartus开发环境下」· RPT 代码 · 共 321 行 · 第 1/4 页

; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~45                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~45                                       ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~47                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~47                                       ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~48                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~48                                       ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~54                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~54                                       ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~55                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~55                                       ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~56                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~56                                       ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~59                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~59                                       ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1                     ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1                          ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|valid_rreq                            ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|valid_rreq                                 ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff                             ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff                                  ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|low_addressa[2]                       ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|low_addressa[2]                            ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|low_addressa[1]                       ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|low_addressa[1]                            ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|low_addressa[0]                       ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|low_addressa[0]                            ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|rd_ptr_lsb                            ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|rd_ptr_lsb                                 ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_is_0_dff                        ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_is_0_dff                             ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_is_1_dff                        ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_is_1_dff                             ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_sua:wr_ptr|counter_cella0        ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_sua:wr_ptr|counter_cella0~COUT        ; cout             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_sua:wr_ptr|counter_cella1        ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_sua:wr_ptr|counter_cella1~COUT        ; cout             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_sua:wr_ptr|counter_cella2        ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_sua:wr_ptr|counter_cella2~COUT        ; cout             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_sua:wr_ptr|counter_cella3        ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_sua:wr_ptr|counter_cella3~COUT        ; cout             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella0 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|safe_q[0]           ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella0 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella0~COUT ; cout             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella1 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|safe_q[1]           ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella1 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella1~COUT ; cout             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella2 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|safe_q[2]           ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella2 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella2~COUT ; cout             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella3 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|safe_q[3]           ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella3 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella3~COUT ; cout             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|counter_cella0    ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|safe_q[0]              ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|counter_cella0    ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|counter_cella0~COUT    ; cout             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|counter_cella1    ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|safe_q[1]              ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|counter_cella1    ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|counter_cella1~COUT    ; cout             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|counter_cella2    ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|counter_cella2~COUT    ; cout             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a0  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0]             ; portbdataout0    ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a1  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[1]             ; portbdataout0    ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a2  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[2]             ; portbdataout0    ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a3  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[3]             ; portbdataout0    ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a4  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[4]             ; portbdataout0    ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a5  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[5]             ; portbdataout0    ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a6  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[6]             ; portbdataout0    ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[7]             ; portbdataout0    ;
+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                                                                        ;
+---------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                       ; Output Port Name                                                                                                           ; Output Port Type ;
+---------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+------------------+
; |lpm_fifo|full                                                                                                                  ; |lpm_fifo|full                                                                                                             ; pin_out          ;
; |lpm_fifo|wrreq                                                                                                                 ; |lpm_fifo|wrreq                                                                                                            ; out              ;
; |lpm_fifo|usedw[4]                                                                                                              ; |lpm_fifo|usedw[4]                                                                                                         ; pin_out          ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~5                                   ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~5                              ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~6                                   ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~6                              ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~9                                   ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~9                              ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~10                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~10                             ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~12                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~12                             ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~18                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~18                             ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~20                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~20                             ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~22                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~22                             ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~23                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~23                             ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|almost_full_comparer_aeb_int~0        ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|almost_full_comparer_aeb_int~0   ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|ram_read_address[4]~0                 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|ram_read_address[4]~0            ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|ram_read_address[2]~2                 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|ram_read_address[2]~2            ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|ram_read_address[0]~4                 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|ram_read_address[0]~4            ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|ram_read_address[4]~5                 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|ram_read_address[4]~5            ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|ram_read_address[4]                   ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|ram_read_address[4]              ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~58                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~58                             ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~60                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~60                             ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~62                                  ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~62                             ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|valid_wreq                            ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|valid_wreq                       ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|wait_state                            ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|wait_state                       ; out0             ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|full_dff                              ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|full_dff                         ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|low_addressa[4]                       ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|low_addressa[4]                  ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|counter_cella4 ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter|safe_q[4] ; regout           ;
; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|counter_cella3    ; |lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb|safe_q[3]    ; regout           ;
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The following table displays output ports that do not toggle to 0 during simulation.