led.tan.qmsg

来自「在quartus开发环境下」· QMSG 代码 · 共 10 行 · 第 1/3 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register q1\[0\] register q1\[3\] 184.43 MHz 5.422 ns Internal " "Info: Clock \"clk\" has Internal fmax of 184.43 MHz between source register \"q1\[0\]\" and destination register \"q1\[3\]\" (period= 5.422 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.159 ns + Longest register register " "Info: + Longest register to register delay is 5.159 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q1\[0\] 1 REG LCFF_X5_Y7_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y7_N5; Fanout = 4; REG Node = 'q1\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { q1[0] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(0.651 ns) 2.594 ns q1~432 2 COMB LCCOMB_X5_Y7_N24 2 " "Info: 2: + IC(1.943 ns) + CELL(0.651 ns) = 2.594 ns; Loc. = LCCOMB_X5_Y7_N24; Fanout = 2; COMB Node = 'q1~432'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.594 ns" { q1[0] q1~432 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.679 ns) + CELL(0.623 ns) 3.896 ns Selector4~59 3 COMB LCCOMB_X6_Y7_N6 1 " "Info: 3: + IC(0.679 ns) + CELL(0.623 ns) = 3.896 ns; Loc. = LCCOMB_X6_Y7_N6; Fanout = 1; COMB Node = 'Selector4~59'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.302 ns" { q1~432 Selector4~59 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.367 ns) + CELL(0.206 ns) 4.469 ns Selector4~60 4 COMB LCCOMB_X6_Y7_N28 1 " "Info: 4: + IC(0.367 ns) + CELL(0.206 ns) = 4.469 ns; Loc. = LCCOMB_X6_Y7_N28; Fanout = 1; COMB Node = 'Selector4~60'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.573 ns" { Selector4~59 Selector4~60 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.206 ns) 5.051 ns Selector4~61 5 COMB LCCOMB_X6_Y7_N8 1 " "Info: 5: + IC(0.376 ns) + CELL(0.206 ns) = 5.051 ns; Loc. = LCCOMB_X6_Y7_N8; Fanout = 1; COMB Node = 'Selector4~61'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.582 ns" { Selector4~60 Selector4~61 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.159 ns q1\[3\] 6 REG LCFF_X6_Y7_N9 4 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 5.159 ns; Loc. = LCFF_X6_Y7_N9; Fanout = 4; REG Node = 'q1\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Selector4~61 q1[3] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.794 ns ( 34.77 % ) " "Info: Total cell delay = 1.794 ns ( 34.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.365 ns ( 65.23 % ) " "Info: Total interconnect delay = 3.365 ns ( 65.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.159 ns" { q1[0] q1~432 Selector4~59 Selector4~60 Selector4~61 q1[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.159 ns" { q1[0] q1~432 Selector4~59 Selector4~60 Selector4~61 q1[3] } { 0.000ns 1.943ns 0.679ns 0.367ns 0.376ns 0.000ns } { 0.000ns 0.651ns 0.623ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.794 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.794 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.000 ns) 1.226 ns clk~clkctrl 2 COMB CLKCTRL_G2 15 " "Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { clk clk~clkctrl } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.902 ns) + CELL(0.666 ns) 2.794 ns q1\[3\] 3 REG LCFF_X6_Y7_N9 4 " "Info: 3: + IC(0.902 ns) + CELL(0.666 ns) = 2.794 ns; Loc. = LCFF_X6_Y7_N9; Fanout = 4; REG Node = 'q1\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { clk~clkctrl q1[3] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.85 % ) " "Info: Total cell delay = 1.756 ns ( 62.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.038 ns ( 37.15 % ) " "Info: Total interconnect delay = 1.038 ns ( 37.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { clk clk~clkctrl q1[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { clk clk~combout clk~clkctrl q1[3] } { 0.000ns 0.000ns 0.136ns 0.902ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.793 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.000 ns) 1.226 ns clk~clkctrl 2 COMB CLKCTRL_G2 15 " "Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { clk clk~clkctrl } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.901 ns) + CELL(0.666 ns) 2.793 ns q1\[0\] 3 REG LCFF_X5_Y7_N5 4 " "Info: 3: + IC(0.901 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X5_Y7_N5; Fanout = 4; REG Node = 'q1\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { clk~clkctrl q1[0] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.87 % ) " "Info: Total cell delay = 1.756 ns ( 62.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 37.13 % ) " "Info: Total interconnect delay = 1.037 ns ( 37.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl q1[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl q1[0] } { 0.000ns 0.000ns 0.136ns 0.901ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { clk clk~clkctrl q1[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { clk clk~combout clk~clkctrl q1[3] } { 0.000ns 0.000ns 0.136ns 0.902ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl q1[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl q1[0] } { 0.000ns 0.000ns 0.136ns 0.901ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.159 ns" { q1[0] q1~432 Selector4~59 Selector4~60 Selector4~61 q1[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.159 ns" { q1[0] q1~432 Selector4~59 Selector4~60 Selector4~61 q1[3] } { 0.000ns 1.943ns 0.679ns 0.367ns 0.376ns 0.000ns } { 0.000ns 0.651ns 0.623ns 0.206ns 0.206ns 0.108ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { clk clk~clkctrl q1[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { clk clk~combout clk~clkctrl q1[3] } { 0.000ns 0.000ns 0.136ns 0.902ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl q1[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl q1[0] } { 0.000ns 0.000ns 0.136ns 0.901ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "count\[0\] rst clk 1.550 ns register " "Info: tsu for register \"count\[0\]\" (data pin = \"rst\", clock pin = \"clk\") is 1.550 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.383 ns + Longest pin register " "Info: + Longest pin to register delay is 4.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns rst 1 PIN PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; PIN Node = 'rst'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.525 ns) + CELL(0.370 ns) 2.985 ns count\[0\]~204 2 COMB LCCOMB_X6_Y7_N30 3 " "Info: 2: + IC(1.525 ns) + CELL(0.370 ns) = 2.985 ns; Loc. = LCCOMB_X6_Y7_N30; Fanout = 3; COMB Node = 'count\[0\]~204'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.895 ns" { rst count[0]~204 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.543 ns) + CELL(0.855 ns) 4.383 ns count\[0\] 3 REG LCFF_X5_Y7_N17 13 " "Info: 3: + IC(0.543 ns) + CELL(0.855 ns) = 4.383 ns; Loc. = LCFF_X5_Y7_N17; Fanout = 13; REG Node = 'count\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.398 ns" { count[0]~204 count[0] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.315 ns ( 52.82 % ) " "Info: Total cell delay = 2.315 ns ( 52.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.068 ns ( 47.18 % ) " "Info: Total interconnect delay = 2.068 ns ( 47.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.383 ns" { rst count[0]~204 count[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "4.383 ns" { rst rst~combout count[0]~204 count[0] } { 0.000ns 0.000ns 1.525ns 0.543ns } { 0.000ns 1.090ns 0.370ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.793 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.000 ns) 1.226 ns clk~clkctrl 2 COMB CLKCTRL_G2 15 " "Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { clk clk~clkctrl } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.901 ns) + CELL(0.666 ns) 2.793 ns count\[0\] 3 REG LCFF_X5_Y7_N17 13 " "Info: 3: + IC(0.901 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X5_Y7_N17; Fanout = 13; REG Node = 'count\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { clk~clkctrl count[0] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.87 % ) " "Info: Total cell delay = 1.756 ns ( 62.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 37.13 % ) " "Info: Total interconnect delay = 1.037 ns ( 37.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl count[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl count[0] } { 0.000ns 0.000ns 0.136ns 0.901ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.383 ns" { rst count[0]~204 count[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "4.383 ns" { rst rst~combout count[0]~204 count[0] } { 0.000ns 0.000ns 1.525ns 0.543ns } { 0.000ns 1.090ns 0.370ns 0.855ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl count[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl count[0] } { 0.000ns 0.000ns 0.136ns 0.901ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[0\] q1\[0\] 8.905 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[0\]\" through register \"q1\[0\]\" is 8.905 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.793 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.000 ns) 1.226 ns clk~clkctrl 2 COMB CLKCTRL_G2 15 " "Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { clk clk~clkctrl } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.901 ns) + CELL(0.666 ns) 2.793 ns q1\[0\] 3 REG LCFF_X5_Y7_N5 4 " "Info: 3: + IC(0.901 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X5_Y7_N5; Fanout = 4; REG Node = 'q1\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { clk~clkctrl q1[0] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.87 % ) " "Info: Total cell delay = 1.756 ns ( 62.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 37.13 % ) " "Info: Total interconnect delay = 1.037 ns ( 37.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl q1[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl q1[0] } { 0.000ns 0.000ns 0.136ns 0.901ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.808 ns + Longest register pin " "Info: + Longest register to pin delay is 5.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q1\[0\] 1 REG LCFF_X5_Y7_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y7_N5; Fanout = 4; REG Node = 'q1\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { q1[0] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.572 ns) + CELL(3.236 ns) 5.808 ns q\[0\] 2 PIN PIN_135 0 " "Info: 2: + IC(2.572 ns) + CELL(3.236 ns) = 5.808 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.808 ns" { q1[0] q[0] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 55.72 % ) " "Info: Total cell delay = 3.236 ns ( 55.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.572 ns ( 44.28 % ) " "Info: Total interconnect delay = 2.572 ns ( 44.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.808 ns" { q1[0] q[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.808 ns" { q1[0] q[0] } { 0.000ns 2.572ns } { 0.000ns 3.236ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl q1[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl q1[0] } { 0.000ns 0.000ns 0.136ns 0.901ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.808 ns" { q1[0] q[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.808 ns" { q1[0] q[0] } { 0.000ns 2.572ns } { 0.000ns 3.236ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "count\[2\] rst clk -0.586 ns register " "Info: th for register \"count\[2\]\" (data pin = \"rst\", clock pin = \"clk\") is -0.586 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.794 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.794 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.000 ns) 1.226 ns clk~clkctrl 2 COMB CLKCTRL_G2 15 " "Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { clk clk~clkctrl } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.902 ns) + CELL(0.666 ns) 2.794 ns count\[2\] 3 REG LCFF_X6_Y7_N15 11 " "Info: 3: + IC(0.902 ns) + CELL(0.666 ns) = 2.794 ns; Loc. = LCFF_X6_Y7_N15; Fanout = 11; REG Node = 'count\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { clk~clkctrl count[2] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.85 % ) " "Info: Total cell delay = 1.756 ns ( 62.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.038 ns ( 37.15 % ) " "Info: Total interconnect delay = 1.038 ns ( 37.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { clk clk~clkctrl count[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { clk clk~combout clk~clkctrl count[2] } { 0.000ns 0.000ns 0.136ns 0.902ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.686 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns rst 1 PIN PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; PIN Node = 'rst'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.525 ns) + CELL(0.370 ns) 2.985 ns count\[0\]~204 2 COMB LCCOMB_X6_Y7_N30 3 " "Info: 2: + IC(1.525 ns) + CELL(0.370 ns) = 2.985 ns; Loc. = LCCOMB_X6_Y7_N30; Fanout = 3; COMB Node = 'count\[0\]~204'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.895 ns" { rst count[0]~204 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.206 ns) 3.578 ns count\[2\]~205 3 COMB LCCOMB_X6_Y7_N14 1 " "Info: 3: + IC(0.387 ns) + CELL(0.206 ns) = 3.578 ns; Loc. = LCCOMB_X6_Y7_N14; Fanout = 1; COMB Node = 'count\[2\]~205'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.593 ns" { count[0]~204 count[2]~205 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.686 ns count\[2\] 4 REG LCFF_X6_Y7_N15 11 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 3.686 ns; Loc. = LCFF_X6_Y7_N15; Fanout = 11; REG Node = 'count\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { count[2]~205 count[2] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/my_eda2/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.774 ns ( 48.13 % ) " "Info: Total cell delay = 1.774 ns ( 48.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.912 ns ( 51.87 % ) " "Info: Total interconnect delay = 1.912 ns ( 51.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.686 ns" { rst count[0]~204 count[2]~205 count[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.686 ns" { rst rst~combout count[0]~204 count[2]~205 count[2] } { 0.000ns 0.000ns 1.525ns 0.387ns 0.000ns } { 0.000ns 1.090ns 0.370ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { clk clk~clkctrl count[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { clk clk~combout clk~clkctrl count[2] } { 0.000ns 0.000ns 0.136ns 0.902ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.686 ns" { rst count[0]~204 count[2]~205 count[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.686 ns" { rst rst~combout count[0]~204 count[2]~205 count[2] } { 0.000ns 0.000ns 1.525ns 0.387ns 0.000ns } { 0.000ns 1.090ns 0.370ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}