led.tan.rpt

来自「在quartus开发环境下」· RPT 代码 · 共 385 行 · 第 1/4 页

; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -0.586 ns ; rst  ; count[2] ; clk      ;
; N/A           ; None        ; -0.587 ns ; rst  ; count[1] ; clk      ;
; N/A           ; None        ; -1.284 ns ; rst  ; count[0] ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Apr 06 16:25:31 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led -c led --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 184.43 MHz between source register "q1[0]" and destination register "q1[3]" (period= 5.422 ns)
    Info: + Longest register to register delay is 5.159 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y7_N5; Fanout = 4; REG Node = 'q1[0]'
        Info: 2: + IC(1.943 ns) + CELL(0.651 ns) = 2.594 ns; Loc. = LCCOMB_X5_Y7_N24; Fanout = 2; COMB Node = 'q1~432'
        Info: 3: + IC(0.679 ns) + CELL(0.623 ns) = 3.896 ns; Loc. = LCCOMB_X6_Y7_N6; Fanout = 1; COMB Node = 'Selector4~59'
        Info: 4: + IC(0.367 ns) + CELL(0.206 ns) = 4.469 ns; Loc. = LCCOMB_X6_Y7_N28; Fanout = 1; COMB Node = 'Selector4~60'
        Info: 5: + IC(0.376 ns) + CELL(0.206 ns) = 5.051 ns; Loc. = LCCOMB_X6_Y7_N8; Fanout = 1; COMB Node = 'Selector4~61'
        Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 5.159 ns; Loc. = LCFF_X6_Y7_N9; Fanout = 4; REG Node = 'q1[3]'
        Info: Total cell delay = 1.794 ns ( 34.77 % )
        Info: Total interconnect delay = 3.365 ns ( 65.23 % )
    Info: - Smallest clock skew is 0.001 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.794 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.902 ns) + CELL(0.666 ns) = 2.794 ns; Loc. = LCFF_X6_Y7_N9; Fanout = 4; REG Node = 'q1[3]'
            Info: Total cell delay = 1.756 ns ( 62.85 % )
            Info: Total interconnect delay = 1.038 ns ( 37.15 % )
        Info: - Longest clock path from clock "clk" to source register is 2.793 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.901 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X5_Y7_N5; Fanout = 4; REG Node = 'q1[0]'
            Info: Total cell delay = 1.756 ns ( 62.87 % )
            Info: Total interconnect delay = 1.037 ns ( 37.13 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "count[0]" (data pin = "rst", clock pin = "clk") is 1.550 ns
    Info: + Longest pin to register delay is 4.383 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; PIN Node = 'rst'
        Info: 2: + IC(1.525 ns) + CELL(0.370 ns) = 2.985 ns; Loc. = LCCOMB_X6_Y7_N30; Fanout = 3; COMB Node = 'count[0]~204'
        Info: 3: + IC(0.543 ns) + CELL(0.855 ns) = 4.383 ns; Loc. = LCFF_X5_Y7_N17; Fanout = 13; REG Node = 'count[0]'
        Info: Total cell delay = 2.315 ns ( 52.82 % )
        Info: Total interconnect delay = 2.068 ns ( 47.18 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.793 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.901 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X5_Y7_N17; Fanout = 13; REG Node = 'count[0]'
        Info: Total cell delay = 1.756 ns ( 62.87 % )
        Info: Total interconnect delay = 1.037 ns ( 37.13 % )
Info: tco from clock "clk" to destination pin "q[0]" through register "q1[0]" is 8.905 ns
    Info: + Longest clock path from clock "clk" to source register is 2.793 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.901 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X5_Y7_N5; Fanout = 4; REG Node = 'q1[0]'
        Info: Total cell delay = 1.756 ns ( 62.87 % )
        Info: Total interconnect delay = 1.037 ns ( 37.13 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.808 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y7_N5; Fanout = 4; REG Node = 'q1[0]'
        Info: 2: + IC(2.572 ns) + CELL(3.236 ns) = 5.808 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'q[0]'
        Info: Total cell delay = 3.236 ns ( 55.72 % )
        Info: Total interconnect delay = 2.572 ns ( 44.28 % )
Info: th for register "count[2]" (data pin = "rst", clock pin = "clk") is -0.586 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.794 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.902 ns) + CELL(0.666 ns) = 2.794 ns; Loc. = LCFF_X6_Y7_N15; Fanout = 11; REG Node = 'count[2]'
        Info: Total cell delay = 1.756 ns ( 62.85 % )
        Info: Total interconnect delay = 1.038 ns ( 37.15 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 3.686 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; PIN Node = 'rst'
        Info: 2: + IC(1.525 ns) + CELL(0.370 ns) = 2.985 ns; Loc. = LCCOMB_X6_Y7_N30; Fanout = 3; COMB Node = 'count[0]~204'
        Info: 3: + IC(0.387 ns) + CELL(0.206 ns) = 3.578 ns; Loc. = LCCOMB_X6_Y7_N14; Fanout = 1; COMB Node = 'count[2]~205'
        Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 3.686 ns; Loc. = LCFF_X6_Y7_N15; Fanout = 11; REG Node = 'count[2]'
        Info: Total cell delay = 1.774 ns ( 48.13 % )
        Info: Total interconnect delay = 1.912 ns ( 51.87 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Fri Apr 06 16:25:32 2007
    Info: Elapsed time: 00:00:01