pll.tan.rpt

在quartus开发环境下

Classic Timing Analyzer report for pll
Wed Apr 25 20:18:46 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. tco
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                        ;
+------------------------------+-------+---------------+-------------+-------------------------------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From                          ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------------------------------+----+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 3.199 ns    ; altpll:altpll_component|_clk1 ; c1 ; inclk0     ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;                               ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+-------------------------------+----+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                ;
+-------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name               ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+-------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; altpll:altpll_component|_clk0 ;                    ; PLL output ; 40.0 MHz         ; 0.000 ns      ; 0.000 ns     ; inclk0   ; 2                     ; 1                   ; -2.438 ns ;              ;
; altpll:altpll_component|_clk1 ;                    ; PLL output ; 80.0 MHz         ; 0.000 ns      ; 0.000 ns     ; inclk0   ; 4                     ; 1                   ; -2.438 ns ;              ;
; altpll:altpll_component|_clk2 ;                    ; PLL output ; 120.0 MHz        ; 0.000 ns      ; 0.000 ns     ; inclk0   ; 6                     ; 1                   ; -2.438 ns ;              ;
; inclk0                        ;                    ; User Pin   ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+-------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-------------------------------------------------------------------------------------+
; tco                                                                                 ;
+-------+--------------+------------+-------------------------------+----+------------+
; Slack ; Required tco ; Actual tco ; From                          ; To ; From Clock ;
+-------+--------------+------------+-------------------------------+----+------------+
; N/A   ; None         ; 3.199 ns   ; altpll:altpll_component|_clk1 ; c1 ; inclk0     ;
; N/A   ; None         ; 3.196 ns   ; altpll:altpll_component|_clk2 ; c2 ; inclk0     ;
; N/A   ; None         ; 1.455 ns   ; altpll:altpll_component|_clk0 ; c0 ; inclk0     ;
+-------+--------------+------------+-------------------------------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Apr 25 20:18:44 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pll -c pll --timing_analysis_only
Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Info: Found timing assignments -- calculating delays
Info: No valid register-to-register data paths exist for clock "altpll:altpll_component|_clk0"
Info: No valid register-to-register data paths exist for clock "altpll:altpll_component|_clk1"
Info: No valid register-to-register data paths exist for clock "altpll:altpll_component|_clk2"
Info: No valid register-to-register data paths exist for clock "inclk0"
Info: tco from clock "inclk0" to destination pin "c1" through clock "altpll:altpll_component|_clk1" is 3.199 ns
    Info: + Offset between input clock "inclk0" and output clock "altpll:altpll_component|_clk1" is -2.438 ns
    Info: + Longest clock to pin delay is 5.637 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll:altpll_component|_clk1'
        Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 1; COMB Node = 'altpll:altpll_component|_clk1~clkctrl'
        Info: 3: + IC(1.485 ns) + CELL(3.236 ns) = 5.637 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'c1'
        Info: Total cell delay = 3.236 ns ( 57.41 % )
        Info: Total interconnect delay = 2.401 ns ( 42.59 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Wed Apr 25 20:18:46 2007
    Info: Elapsed time: 00:00:02