pll.hier_info

在quartus开发环境下

|pll
areset => altpll:altpll_component.areset
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]
c1 <= altpll:altpll_component.clk[1]
c2 <= altpll:altpll_component.clk[2]
locked <= altpll:altpll_component.locked


|pll|altpll:altpll_component
inclk[0] => cycloneii_pll:pll.INCLK[0]
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => cycloneii_pll:pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
clk[0] <= clk[0]~2.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1]~1.DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= _locked.DB_MAX_OUTPUT_PORT_TYPE
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>