jp4x4_1.tan.qmsg

在quartus开发环境下

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "7 " "Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "dat\[3\] " "Info: Detected ripple clock \"dat\[3\]\" as buffer" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "dat\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "dat\[4\] " "Info: Detected ripple clock \"dat\[4\]\" as buffer" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "dat\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "fn~33 " "Info: Detected gated clock \"fn~33\" as buffer" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 17 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "fn~33" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "dat\[0\] " "Info: Detected ripple clock \"dat\[0\]\" as buffer" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "dat\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "dat\[2\] " "Info: Detected ripple clock \"dat\[2\]\" as buffer" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "dat\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "dat\[1\] " "Info: Detected ripple clock \"dat\[1\]\" as buffer" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "dat\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "fn~3 " "Info: Detected gated clock \"fn~3\" as buffer" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 17 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "fn~3" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register sta\[0\] seg7\[2\] 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"sta\[0\]\" and destination register \"seg7\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.669 ns + Longest register register " "Info: + Longest register to register delay is 1.669 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sta\[0\] 1 REG LCFF_X15_Y12_N11 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y12_N11; Fanout = 15; REG Node = 'sta\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { sta[0] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.492 ns) + CELL(0.206 ns) 0.698 ns Mux23~13 2 COMB LCCOMB_X15_Y12_N4 1 " "Info: 2: + IC(0.492 ns) + CELL(0.206 ns) = 0.698 ns; Loc. = LCCOMB_X15_Y12_N4; Fanout = 1; COMB Node = 'Mux23~13'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.698 ns" { sta[0] Mux23~13 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.657 ns) + CELL(0.206 ns) 1.561 ns Mux23~14 3 COMB LCCOMB_X15_Y12_N2 1 " "Info: 3: + IC(0.657 ns) + CELL(0.206 ns) = 1.561 ns; Loc. = LCCOMB_X15_Y12_N2; Fanout = 1; COMB Node = 'Mux23~14'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.863 ns" { Mux23~13 Mux23~14 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.669 ns seg7\[2\] 4 REG LCFF_X15_Y12_N3 1 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.669 ns; Loc. = LCFF_X15_Y12_N3; Fanout = 1; REG Node = 'seg7\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Mux23~14 seg7[2] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.520 ns ( 31.16 % ) " "Info: Total cell delay = 0.520 ns ( 31.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.149 ns ( 68.84 % ) " "Info: Total interconnect delay = 1.149 ns ( 68.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.669 ns" { sta[0] Mux23~13 Mux23~14 seg7[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "1.669 ns" { sta[0] Mux23~13 Mux23~14 seg7[2] } { 0.000ns 0.492ns 0.657ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.801 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 19 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 2.801 ns seg7\[2\] 3 REG LCFF_X15_Y12_N3 1 " "Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X15_Y12_N3; Fanout = 1; REG Node = 'seg7\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { clk~clkctrl seg7[2] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.69 % ) " "Info: Total cell delay = 1.756 ns ( 62.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.045 ns ( 37.31 % ) " "Info: Total interconnect delay = 1.045 ns ( 37.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl seg7[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl seg7[2] } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.801 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 19 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 2.801 ns sta\[0\] 3 REG LCFF_X15_Y12_N11 15 " "Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X15_Y12_N11; Fanout = 15; REG Node = 'sta\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { clk~clkctrl sta[0] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.69 % ) " "Info: Total cell delay = 1.756 ns ( 62.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.045 ns ( 37.31 % ) " "Info: Total interconnect delay = 1.045 ns ( 37.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl sta[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl sta[0] } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl seg7[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl seg7[2] } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl sta[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl sta[0] } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.669 ns" { sta[0] Mux23~13 Mux23~14 seg7[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "1.669 ns" { sta[0] Mux23~13 Mux23~14 seg7[2] } { 0.000ns 0.492ns 0.657ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.108ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl seg7[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl seg7[2] } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl sta[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl sta[0] } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { seg7[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { seg7[2] } {  } {  } "" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 7 " "Warning: Circuit may not operate. Detected 7 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "seg7\[4\] seg7_out\[4\]~reg0 clk 4.43 ns " "Info: Found hold time violation between source  pin or register \"seg7\[4\]\" and destination pin or register \"seg7_out\[4\]~reg0\" for clock \"clk\" (Hold time is 4.43 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.835 ns + Largest " "Info: + Largest clock skew is 5.835 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.636 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 19 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.970 ns) 3.105 ns dat\[3\] 3 REG LCFF_X15_Y12_N31 1 " "Info: 3: + IC(0.906 ns) + CELL(0.970 ns) = 3.105 ns; Loc. = LCFF_X15_Y12_N31; Fanout = 1; REG Node = 'dat\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.876 ns" { clk~clkctrl dat[3] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.206 ns) 4.040 ns fn~33 4 COMB LCCOMB_X14_Y12_N22 1 " "Info: 4: + IC(0.729 ns) + CELL(0.206 ns) = 4.040 ns; Loc. = LCCOMB_X14_Y12_N22; Fanout = 1; COMB Node = 'fn~33'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.935 ns" { dat[3] fn~33 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.206 ns) 4.600 ns fn~3 5 COMB LCCOMB_X14_Y12_N14 1 " "Info: 5: + IC(0.354 ns) + CELL(0.206 ns) = 4.600 ns; Loc. = LCCOMB_X14_Y12_N14; Fanout = 1; COMB Node = 'fn~3'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.560 ns" { fn~33 fn~3 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.485 ns) + CELL(0.000 ns) 7.085 ns fn~3clkctrl 6 COMB CLKCTRL_G0 7 " "Info: 6: + IC(2.485 ns) + CELL(0.000 ns) = 7.085 ns; Loc. = CLKCTRL_G0; Fanout = 7; COMB Node = 'fn~3clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { fn~3 fn~3clkctrl } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.885 ns) + CELL(0.666 ns) 8.636 ns seg7_out\[4\]~reg0 7 REG LCFF_X19_Y12_N13 1 " "Info: 7: + IC(0.885 ns) + CELL(0.666 ns) = 8.636 ns; Loc. = LCFF_X19_Y12_N13; Fanout = 1; REG Node = 'seg7_out\[4\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { fn~3clkctrl seg7_out[4]~reg0 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 85 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.138 ns ( 36.34 % ) " "Info: Total cell delay = 3.138 ns ( 36.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.498 ns ( 63.66 % ) " "Info: Total interconnect delay = 5.498 ns ( 63.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.636 ns" { clk clk~clkctrl dat[3] fn~33 fn~3 fn~3clkctrl seg7_out[4]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.636 ns" { clk clk~combout clk~clkctrl dat[3] fn~33 fn~3 fn~3clkctrl seg7_out[4]~reg0 } { 0.000ns 0.000ns 0.139ns 0.906ns 0.729ns 0.354ns 2.485ns 0.885ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.206ns 0.206ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.801 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 19 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 2.801 ns seg7\[4\] 3 REG LCFF_X15_Y12_N25 1 " "Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X15_Y12_N25; Fanout = 1; REG Node = 'seg7\[4\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { clk~clkctrl seg7[4] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.69 % ) " "Info: Total cell delay = 1.756 ns ( 62.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.045 ns ( 37.31 % ) " "Info: Total interconnect delay = 1.045 ns ( 37.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl seg7[4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl seg7[4] } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.636 ns" { clk clk~clkctrl dat[3] fn~33 fn~3 fn~3clkctrl seg7_out[4]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.636 ns" { clk clk~combout clk~clkctrl dat[3] fn~33 fn~3 fn~3clkctrl seg7_out[4]~reg0 } { 0.000ns 0.000ns 0.139ns 0.906ns 0.729ns 0.354ns 2.485ns 0.885ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.206ns 0.206ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl seg7[4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl seg7[4] } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.407 ns - Shortest register register " "Info: - Shortest register to register delay is 1.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seg7\[4\] 1 REG LCFF_X15_Y12_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y12_N25; Fanout = 1; REG Node = 'seg7\[4\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { seg7[4] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.093 ns) + CELL(0.206 ns) 1.299 ns seg7_out\[4\]~reg0feeder 2 COMB LCCOMB_X19_Y12_N12 1 " "Info: 2: + IC(1.093 ns) + CELL(0.206 ns) = 1.299 ns; Loc. = LCCOMB_X19_Y12_N12; Fanout = 1; COMB Node = 'seg7_out\[4\]~reg0feeder'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { seg7[4] seg7_out[4]~reg0feeder } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.407 ns seg7_out\[4\]~reg0 3 REG LCFF_X19_Y12_N13 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.407 ns; Loc. = LCFF_X19_Y12_N13; Fanout = 1; REG Node = 'seg7_out\[4\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { seg7_out[4]~reg0feeder seg7_out[4]~reg0 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 85 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 22.32 % ) " "Info: Total cell delay = 0.314 ns ( 22.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.093 ns ( 77.68 % ) " "Info: Total interconnect delay = 1.093 ns ( 77.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.407 ns" { seg7[4] seg7_out[4]~reg0feeder seg7_out[4]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "1.407 ns" { seg7[4] seg7_out[4]~reg0feeder seg7_out[4]~reg0 } { 0.000ns 1.093ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 85 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.636 ns" { clk clk~clkctrl dat[3] fn~33 fn~3 fn~3clkctrl seg7_out[4]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.636 ns" { clk clk~combout clk~clkctrl dat[3] fn~33 fn~3 fn~3clkctrl seg7_out[4]~reg0 } { 0.000ns 0.000ns 0.139ns 0.906ns 0.729ns 0.354ns 2.485ns 0.885ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.206ns 0.206ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl seg7[4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl seg7[4] } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.407 ns" { seg7[4] seg7_out[4]~reg0feeder seg7_out[4]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "1.407 ns" { seg7[4] seg7_out[4]~reg0feeder seg7_out[4]~reg0 } { 0.000ns 1.093ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}