sin.tan.rpt

在quartus开发环境下

; N/A   ; None         ; 8.057 ns   ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[6] ; q[6] ; clock      ;
; N/A   ; None         ; 8.041 ns   ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] ; q[0] ; clock      ;
; N/A   ; None         ; 7.719 ns   ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[7] ; q[7] ; clock      ;
; N/A   ; None         ; 7.352 ns   ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[1] ; q[1] ; clock      ;
+-------+--------------+------------+------------------------------------------------------------------------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Apr 26 10:49:17 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sin -c sin --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 180.05 MHz between source memory "sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0" and destination memory "sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0]"
    Info: fmax restricted to Clock High delay (2.777 ns) plus Clock Low delay (2.777 ns) : restricted to 5.554 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 3.641 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y2; Fanout = 8; MEM Node = 'sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0'
            Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X11_Y2; Fanout = 1; MEM Node = 'sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0]'
            Info: Total cell delay = 3.641 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.020 ns
            Info: + Shortest clock path from clock "clock" to destination memory is 2.900 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 20; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.856 ns) + CELL(0.815 ns) = 2.900 ns; Loc. = M4K_X11_Y2; Fanout = 1; MEM Node = 'sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0]'
                Info: Total cell delay = 1.905 ns ( 65.69 % )
                Info: Total interconnect delay = 0.995 ns ( 34.31 % )
            Info: - Longest clock path from clock "clock" to source memory is 2.920 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 20; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.856 ns) + CELL(0.835 ns) = 2.920 ns; Loc. = M4K_X11_Y2; Fanout = 8; MEM Node = 'sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0'
                Info: Total cell delay = 1.925 ns ( 65.92 % )
                Info: Total interconnect delay = 0.995 ns ( 34.08 % )
        Info: + Micro clock to output delay of source is 0.260 ns
        Info: + Micro setup delay of destination is 0.046 ns
Info: tco from clock "clock" to destination pin "q[3]" through memory "sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3]" is 9.061 ns
    Info: + Longest clock path from clock "clock" to source memory is 2.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 20; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.856 ns) + CELL(0.815 ns) = 2.900 ns; Loc. = M4K_X11_Y2; Fanout = 1; MEM Node = 'sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3]'
        Info: Total cell delay = 1.905 ns ( 65.69 % )
        Info: Total interconnect delay = 0.995 ns ( 34.31 % )
    Info: + Micro clock to output delay of source is 0.260 ns
    Info: + Longest memory to pin delay is 5.901 ns
        Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X11_Y2; Fanout = 1; MEM Node = 'sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3]'
        Info: 2: + IC(2.566 ns) + CELL(3.226 ns) = 5.901 ns; Loc. = PIN_132; Fanout = 0; PIN Node = 'q[3]'
        Info: Total cell delay = 3.335 ns ( 56.52 % )
        Info: Total interconnect delay = 2.566 ns ( 43.48 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Thu Apr 26 10:49:19 2007
    Info: Elapsed time: 00:00:02