sin.tan.rpt

在quartus开发环境下

; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                        ; To                                                                                                          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;