📄 sin.map.rpt
字号:
; -- arithmetic mode ; 4 ;
; ; ;
; Total registers ; 6 ;
; -- Dedicated logic registers ; 6 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 0 ;
; Total memory bits ; 512 ;
; Maximum fan-out node ; clock ;
; Maximum fan-out ; 14 ;
; Total fan-out ; 87 ;
; Average fan-out ; 3.00 ;
+---------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------+
; |sin ; 6 (0) ; 6 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sin ;
; |cnt:inst2| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sin|cnt:inst2 ;
; |sin_rom:inst| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sin|sin_rom:inst ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sin|sin_rom:inst|altsyncram:altsyncram_component ;
; |altsyncram_4871:auto_generated| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sin|sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------+
; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 64 ; 8 ; -- ; -- ; 512 ; sin_data.mif ;
+----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 6 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------+
; Source assignments for sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+--------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+--------------------------------------+
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sin_rom:inst|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+-------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+-------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 8 ; Signed Integer ;
; WIDTHAD_A ; 6 ; Signed Integer ;
; NUMWORDS_A ; 64 ; Signed Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; sin_data.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_4871 ; Untyped ;
+------------------------------------+----------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Thu Apr 26 10:48:32 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin -c sin
Info: Found 2 design units, including 1 entities, in source file cnt.vhd
Info: Found design unit 1: cnt-one
Info: Found entity 1: cnt
Info: Found 1 design units, including 1 entities, in source file sin.bdf
Info: Found entity 1: sin
Info: Elaborating entity "sin" for the top level hierarchy
Warning: Using design file sin_rom.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: sin_rom-SYN
Info: Found entity 1: sin_rom
Info: Elaborating entity "sin_rom" for hierarchy "sin_rom:inst"
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus ii7.0/quartus/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "sin_rom:inst|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "sin_rom:inst|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4871.tdf
Info: Found entity 1: altsyncram_4871
Info: Elaborating entity "altsyncram_4871" for hierarchy "sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated"
Info: Elaborating entity "cnt" for hierarchy "cnt:inst2"
Info: Implemented 23 device resources after synthesis - the final resource count might be different
Info: Implemented 1 input pins
Info: Implemented 8 output pins
Info: Implemented 6 logic cells
Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 144 megabytes of memory during processing
Info: Processing ended: Thu Apr 26 10:48:37 2007
Info: Elapsed time: 00:00:05
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -