jiao_tong.tan.qmsg

在quartus开发环境下

{ "Info" "ITDB_FULL_TPD_RESULT" "jin seg7\[4\] 14.352 ns Longest " "Info: Longest tpd from source pin \"jin\" to destination pin \"seg7\[4\]\" is 14.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns jin 1 PIN PIN_63 25 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_63; Fanout = 25; PIN Node = 'jin'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { jin } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.745 ns) + CELL(0.370 ns) 9.059 ns seg7~249 2 COMB LCCOMB_X14_Y11_N8 1 " "Info: 2: + IC(7.745 ns) + CELL(0.370 ns) = 9.059 ns; Loc. = LCCOMB_X14_Y11_N8; Fanout = 1; COMB Node = 'seg7~249'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.115 ns" { jin seg7~249 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.067 ns) + CELL(3.226 ns) 14.352 ns seg7\[4\] 3 PIN PIN_125 0 " "Info: 3: + IC(2.067 ns) + CELL(3.226 ns) = 14.352 ns; Loc. = PIN_125; Fanout = 0; PIN Node = 'seg7\[4\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.293 ns" { seg7~249 seg7[4] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.540 ns ( 31.63 % ) " "Info: Total cell delay = 4.540 ns ( 31.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.812 ns ( 68.37 % ) " "Info: Total interconnect delay = 9.812 ns ( 68.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "14.352 ns" { jin seg7~249 seg7[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "14.352 ns" { jin jin~combout seg7~249 seg7[4] } { 0.000ns 0.000ns 7.745ns 2.067ns } { 0.000ns 0.944ns 0.370ns 3.226ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ql\[2\] jin clk -2.463 ns register " "Info: th for register \"ql\[2\]\" (data pin = \"jin\", clock pin = \"clk\") is -2.463 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.330 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.970 ns) 2.592 ns clk1khz 2 REG LCFF_X1_Y9_N9 2 " "Info: 2: + IC(0.532 ns) + CELL(0.970 ns) = 2.592 ns; Loc. = LCFF_X1_Y9_N9; Fanout = 2; REG Node = 'clk1khz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.502 ns" { clk clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.970 ns) 3.948 ns clk1hz 3 REG LCFF_X1_Y9_N27 15 " "Info: 3: + IC(0.386 ns) + CELL(0.970 ns) = 3.948 ns; Loc. = LCFF_X1_Y9_N27; Fanout = 15; REG Node = 'clk1hz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.356 ns" { clk1khz clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.000 ns) 4.771 ns clk1hz~clkctrl 4 COMB CLKCTRL_G1 18 " "Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.771 ns; Loc. = CLKCTRL_G1; Fanout = 18; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.823 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.666 ns) 6.330 ns ql\[2\] 5 REG LCFF_X13_Y11_N13 5 " "Info: 5: + IC(0.893 ns) + CELL(0.666 ns) = 6.330 ns; Loc. = LCFF_X13_Y11_N13; Fanout = 5; REG Node = 'ql\[2\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { clk1hz~clkctrl ql[2] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 58.39 % ) " "Info: Total cell delay = 3.696 ns ( 58.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.634 ns ( 41.61 % ) " "Info: Total interconnect delay = 2.634 ns ( 41.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk clk1khz clk1hz clk1hz~clkctrl ql[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl ql[2] } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.099 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns jin 1 PIN PIN_63 25 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_63; Fanout = 25; PIN Node = 'jin'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { jin } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.300 ns) + CELL(0.855 ns) 9.099 ns ql\[2\] 2 REG LCFF_X13_Y11_N13 5 " "Info: 2: + IC(7.300 ns) + CELL(0.855 ns) = 9.099 ns; Loc. = LCFF_X13_Y11_N13; Fanout = 5; REG Node = 'ql\[2\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.155 ns" { jin ql[2] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.799 ns ( 19.77 % ) " "Info: Total cell delay = 1.799 ns ( 19.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.300 ns ( 80.23 % ) " "Info: Total interconnect delay = 7.300 ns ( 80.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.099 ns" { jin ql[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.099 ns" { jin jin~combout ql[2] } { 0.000ns 0.000ns 7.300ns } { 0.000ns 0.944ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk clk1khz clk1hz clk1hz~clkctrl ql[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl ql[2] } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.099 ns" { jin ql[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.099 ns" { jin jin~combout ql[2] } { 0.000ns 0.000ns 7.300ns } { 0.000ns 0.944ns 0.855ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 01 16:23:42 2007 " "Info: Processing ended: Fri Jun 01 16:23:42 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}