jiao_tong.tan.qmsg

在quartus开发环境下

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1khz " "Info: Detected ripple clock \"clk1khz\" as buffer" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1khz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk1hz " "Info: Detected ripple clock \"clk1hz\" as buffer" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register stx.st1 register qh\[1\] 237.64 MHz 4.208 ns Internal " "Info: Clock \"clk\" has Internal fmax of 237.64 MHz between source register \"stx.st1\" and destination register \"qh\[1\]\" (period= 4.208 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.944 ns + Longest register register " "Info: + Longest register to register delay is 3.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns stx.st1 1 REG LCFF_X14_Y11_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y11_N5; Fanout = 5; REG Node = 'stx.st1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { stx.st1 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.366 ns) 0.821 ns qh\[1\]~488 2 COMB LCCOMB_X14_Y11_N6 2 " "Info: 2: + IC(0.455 ns) + CELL(0.366 ns) = 0.821 ns; Loc. = LCCOMB_X14_Y11_N6; Fanout = 2; COMB Node = 'qh\[1\]~488'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.821 ns" { stx.st1 qh[1]~488 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.647 ns) 2.171 ns qh\[1\]~489 3 COMB LCCOMB_X13_Y11_N28 1 " "Info: 3: + IC(0.703 ns) + CELL(0.647 ns) = 2.171 ns; Loc. = LCCOMB_X13_Y11_N28; Fanout = 1; COMB Node = 'qh\[1\]~489'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.350 ns" { qh[1]~488 qh[1]~489 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.382 ns) + CELL(0.206 ns) 2.759 ns qh\[1\]~490 4 COMB LCCOMB_X13_Y11_N6 3 " "Info: 4: + IC(0.382 ns) + CELL(0.206 ns) = 2.759 ns; Loc. = LCCOMB_X13_Y11_N6; Fanout = 3; COMB Node = 'qh\[1\]~490'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.588 ns" { qh[1]~489 qh[1]~490 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.330 ns) + CELL(0.855 ns) 3.944 ns qh\[1\] 5 REG LCFF_X13_Y11_N11 5 " "Info: 5: + IC(0.330 ns) + CELL(0.855 ns) = 3.944 ns; Loc. = LCFF_X13_Y11_N11; Fanout = 5; REG Node = 'qh\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.185 ns" { qh[1]~490 qh[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.074 ns ( 52.59 % ) " "Info: Total cell delay = 2.074 ns ( 52.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.870 ns ( 47.41 % ) " "Info: Total interconnect delay = 1.870 ns ( 47.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.944 ns" { stx.st1 qh[1]~488 qh[1]~489 qh[1]~490 qh[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.944 ns" { stx.st1 qh[1]~488 qh[1]~489 qh[1]~490 qh[1] } { 0.000ns 0.455ns 0.703ns 0.382ns 0.330ns } { 0.000ns 0.366ns 0.647ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.330 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.970 ns) 2.592 ns clk1khz 2 REG LCFF_X1_Y9_N9 2 " "Info: 2: + IC(0.532 ns) + CELL(0.970 ns) = 2.592 ns; Loc. = LCFF_X1_Y9_N9; Fanout = 2; REG Node = 'clk1khz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.502 ns" { clk clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.970 ns) 3.948 ns clk1hz 3 REG LCFF_X1_Y9_N27 15 " "Info: 3: + IC(0.386 ns) + CELL(0.970 ns) = 3.948 ns; Loc. = LCFF_X1_Y9_N27; Fanout = 15; REG Node = 'clk1hz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.356 ns" { clk1khz clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.000 ns) 4.771 ns clk1hz~clkctrl 4 COMB CLKCTRL_G1 18 " "Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.771 ns; Loc. = CLKCTRL_G1; Fanout = 18; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.823 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.666 ns) 6.330 ns qh\[1\] 5 REG LCFF_X13_Y11_N11 5 " "Info: 5: + IC(0.893 ns) + CELL(0.666 ns) = 6.330 ns; Loc. = LCFF_X13_Y11_N11; Fanout = 5; REG Node = 'qh\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { clk1hz~clkctrl qh[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 58.39 % ) " "Info: Total cell delay = 3.696 ns ( 58.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.634 ns ( 41.61 % ) " "Info: Total interconnect delay = 2.634 ns ( 41.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk clk1khz clk1hz clk1hz~clkctrl qh[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl qh[1] } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.330 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.970 ns) 2.592 ns clk1khz 2 REG LCFF_X1_Y9_N9 2 " "Info: 2: + IC(0.532 ns) + CELL(0.970 ns) = 2.592 ns; Loc. = LCFF_X1_Y9_N9; Fanout = 2; REG Node = 'clk1khz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.502 ns" { clk clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.970 ns) 3.948 ns clk1hz 3 REG LCFF_X1_Y9_N27 15 " "Info: 3: + IC(0.386 ns) + CELL(0.970 ns) = 3.948 ns; Loc. = LCFF_X1_Y9_N27; Fanout = 15; REG Node = 'clk1hz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.356 ns" { clk1khz clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.000 ns) 4.771 ns clk1hz~clkctrl 4 COMB CLKCTRL_G1 18 " "Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.771 ns; Loc. = CLKCTRL_G1; Fanout = 18; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.823 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.666 ns) 6.330 ns stx.st1 5 REG LCFF_X14_Y11_N5 5 " "Info: 5: + IC(0.893 ns) + CELL(0.666 ns) = 6.330 ns; Loc. = LCFF_X14_Y11_N5; Fanout = 5; REG Node = 'stx.st1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { clk1hz~clkctrl stx.st1 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 58.39 % ) " "Info: Total cell delay = 3.696 ns ( 58.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.634 ns ( 41.61 % ) " "Info: Total interconnect delay = 2.634 ns ( 41.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk clk1khz clk1hz clk1hz~clkctrl stx.st1 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl stx.st1 } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk clk1khz clk1hz clk1hz~clkctrl qh[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl qh[1] } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk clk1khz clk1hz clk1hz~clkctrl stx.st1 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl stx.st1 } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.944 ns" { stx.st1 qh[1]~488 qh[1]~489 qh[1]~490 qh[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.944 ns" { stx.st1 qh[1]~488 qh[1]~489 qh[1]~490 qh[1] } { 0.000ns 0.455ns 0.703ns 0.382ns 0.330ns } { 0.000ns 0.366ns 0.647ns 0.206ns 0.855ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk clk1khz clk1hz clk1hz~clkctrl qh[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl qh[1] } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk clk1khz clk1hz clk1hz~clkctrl stx.st1 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl stx.st1 } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "r1 jin clk 4.109 ns register " "Info: tsu for register \"r1\" (data pin = \"jin\", clock pin = \"clk\") is 4.109 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.474 ns + Longest pin register " "Info: + Longest pin to register delay is 10.474 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns jin 1 PIN PIN_63 25 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_63; Fanout = 25; PIN Node = 'jin'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { jin } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.811 ns) + CELL(0.537 ns) 9.292 ns r1~47 2 COMB LCCOMB_X10_Y11_N12 5 " "Info: 2: + IC(7.811 ns) + CELL(0.537 ns) = 9.292 ns; Loc. = LCCOMB_X10_Y11_N12; Fanout = 5; COMB Node = 'r1~47'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.348 ns" { jin r1~47 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.327 ns) + CELL(0.855 ns) 10.474 ns r1 3 REG LCFF_X10_Y11_N11 2 " "Info: 3: + IC(0.327 ns) + CELL(0.855 ns) = 10.474 ns; Loc. = LCFF_X10_Y11_N11; Fanout = 2; REG Node = 'r1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.182 ns" { r1~47 r1 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 22.30 % ) " "Info: Total cell delay = 2.336 ns ( 22.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.138 ns ( 77.70 % ) " "Info: Total interconnect delay = 8.138 ns ( 77.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.474 ns" { jin r1~47 r1 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.474 ns" { jin jin~combout r1~47 r1 } { 0.000ns 0.000ns 7.811ns 0.327ns } { 0.000ns 0.944ns 0.537ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.325 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.325 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.970 ns) 2.592 ns clk1khz 2 REG LCFF_X1_Y9_N9 2 " "Info: 2: + IC(0.532 ns) + CELL(0.970 ns) = 2.592 ns; Loc. = LCFF_X1_Y9_N9; Fanout = 2; REG Node = 'clk1khz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.502 ns" { clk clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.970 ns) 3.948 ns clk1hz 3 REG LCFF_X1_Y9_N27 15 " "Info: 3: + IC(0.386 ns) + CELL(0.970 ns) = 3.948 ns; Loc. = LCFF_X1_Y9_N27; Fanout = 15; REG Node = 'clk1hz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.356 ns" { clk1khz clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.000 ns) 4.771 ns clk1hz~clkctrl 4 COMB CLKCTRL_G1 18 " "Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.771 ns; Loc. = CLKCTRL_G1; Fanout = 18; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.823 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.666 ns) 6.325 ns r1 5 REG LCFF_X10_Y11_N11 2 " "Info: 5: + IC(0.888 ns) + CELL(0.666 ns) = 6.325 ns; Loc. = LCFF_X10_Y11_N11; Fanout = 2; REG Node = 'r1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.554 ns" { clk1hz~clkctrl r1 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 58.43 % ) " "Info: Total cell delay = 3.696 ns ( 58.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.629 ns ( 41.57 % ) " "Info: Total interconnect delay = 2.629 ns ( 41.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.325 ns" { clk clk1khz clk1hz clk1hz~clkctrl r1 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.325 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl r1 } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.888ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.474 ns" { jin r1~47 r1 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.474 ns" { jin jin~combout r1~47 r1 } { 0.000ns 0.000ns 7.811ns 0.327ns } { 0.000ns 0.944ns 0.537ns 0.855ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.325 ns" { clk clk1khz clk1hz clk1hz~clkctrl r1 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.325 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl r1 } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.888ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg7\[4\] qh\[1\] 16.748 ns register " "Info: tco from clock \"clk\" to destination pin \"seg7\[4\]\" through register \"qh\[1\]\" is 16.748 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.330 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.970 ns) 2.592 ns clk1khz 2 REG LCFF_X1_Y9_N9 2 " "Info: 2: + IC(0.532 ns) + CELL(0.970 ns) = 2.592 ns; Loc. = LCFF_X1_Y9_N9; Fanout = 2; REG Node = 'clk1khz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.502 ns" { clk clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.970 ns) 3.948 ns clk1hz 3 REG LCFF_X1_Y9_N27 15 " "Info: 3: + IC(0.386 ns) + CELL(0.970 ns) = 3.948 ns; Loc. = LCFF_X1_Y9_N27; Fanout = 15; REG Node = 'clk1hz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.356 ns" { clk1khz clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.000 ns) 4.771 ns clk1hz~clkctrl 4 COMB CLKCTRL_G1 18 " "Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.771 ns; Loc. = CLKCTRL_G1; Fanout = 18; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.823 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.666 ns) 6.330 ns qh\[1\] 5 REG LCFF_X13_Y11_N11 5 " "Info: 5: + IC(0.893 ns) + CELL(0.666 ns) = 6.330 ns; Loc. = LCFF_X13_Y11_N11; Fanout = 5; REG Node = 'qh\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { clk1hz~clkctrl qh[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 58.39 % ) " "Info: Total cell delay = 3.696 ns ( 58.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.634 ns ( 41.61 % ) " "Info: Total interconnect delay = 2.634 ns ( 41.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk clk1khz clk1hz clk1hz~clkctrl qh[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl qh[1] } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.114 ns + Longest register pin " "Info: + Longest register to pin delay is 10.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qh\[1\] 1 REG LCFF_X13_Y11_N11 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y11_N11; Fanout = 5; REG Node = 'qh\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { qh[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.882 ns) + CELL(0.370 ns) 2.252 ns Mux11~14 2 COMB LCCOMB_X12_Y11_N6 7 " "Info: 2: + IC(1.882 ns) + CELL(0.370 ns) = 2.252 ns; Loc. = LCCOMB_X12_Y11_N6; Fanout = 7; COMB Node = 'Mux11~14'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.252 ns" { qh[1] Mux11~14 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 187 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(0.624 ns) 3.943 ns Mux6~23 3 COMB LCCOMB_X14_Y11_N24 1 " "Info: 3: + IC(1.067 ns) + CELL(0.624 ns) = 3.943 ns; Loc. = LCCOMB_X14_Y11_N24; Fanout = 1; COMB Node = 'Mux6~23'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.691 ns" { Mux11~14 Mux6~23 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 196 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.676 ns) + CELL(0.202 ns) 4.821 ns seg7~249 4 COMB LCCOMB_X14_Y11_N8 1 " "Info: 4: + IC(0.676 ns) + CELL(0.202 ns) = 4.821 ns; Loc. = LCCOMB_X14_Y11_N8; Fanout = 1; COMB Node = 'seg7~249'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.878 ns" { Mux6~23 seg7~249 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.067 ns) + CELL(3.226 ns) 10.114 ns seg7\[4\] 5 PIN PIN_125 0 " "Info: 5: + IC(2.067 ns) + CELL(3.226 ns) = 10.114 ns; Loc. = PIN_125; Fanout = 0; PIN Node = 'seg7\[4\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.293 ns" { seg7~249 seg7[4] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.422 ns ( 43.72 % ) " "Info: Total cell delay = 4.422 ns ( 43.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.692 ns ( 56.28 % ) " "Info: Total interconnect delay = 5.692 ns ( 56.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.114 ns" { qh[1] Mux11~14 Mux6~23 seg7~249 seg7[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.114 ns" { qh[1] Mux11~14 Mux6~23 seg7~249 seg7[4] } { 0.000ns 1.882ns 1.067ns 0.676ns 2.067ns } { 0.000ns 0.370ns 0.624ns 0.202ns 3.226ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk clk1khz clk1hz clk1hz~clkctrl qh[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk clk~combout clk1khz clk1hz clk1hz~clkctrl qh[1] } { 0.000ns 0.000ns 0.532ns 0.386ns 0.823ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.114 ns" { qh[1] Mux11~14 Mux6~23 seg7~249 seg7[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.114 ns" { qh[1] Mux11~14 Mux6~23 seg7~249 seg7[4] } { 0.000ns 1.882ns 1.067ns 0.676ns 2.067ns } { 0.000ns 0.370ns 0.624ns 0.202ns 3.226ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}