jiao_tong.tan.rpt

在quartus开发环境下

+---------------+-------------+-----------+------+---------+----------+
; N/A           ; None        ; -2.463 ns ; jin  ; ql[2]   ; clk      ;
; N/A           ; None        ; -2.463 ns ; jin  ; ql[3]   ; clk      ;
; N/A           ; None        ; -2.463 ns ; jin  ; ql[0]   ; clk      ;
; N/A           ; None        ; -2.463 ns ; jin  ; ql[1]   ; clk      ;
; N/A           ; None        ; -2.474 ns ; jin  ; qh[0]   ; clk      ;
; N/A           ; None        ; -2.860 ns ; jin  ; a       ; clk      ;
; N/A           ; None        ; -3.239 ns ; jin  ; stx.st2 ; clk      ;
; N/A           ; None        ; -3.241 ns ; jin  ; stx.st1 ; clk      ;
; N/A           ; None        ; -3.242 ns ; jin  ; stx.st4 ; clk      ;
; N/A           ; None        ; -3.402 ns ; jin  ; qh[1]   ; clk      ;
; N/A           ; None        ; -3.402 ns ; jin  ; qh[2]   ; clk      ;
; N/A           ; None        ; -3.402 ns ; jin  ; qh[3]   ; clk      ;
; N/A           ; None        ; -3.580 ns ; jin  ; stx.st3 ; clk      ;
; N/A           ; None        ; -3.843 ns ; jin  ; r1      ; clk      ;
; N/A           ; None        ; -3.843 ns ; jin  ; y1      ; clk      ;
; N/A           ; None        ; -3.843 ns ; jin  ; g1      ; clk      ;
; N/A           ; None        ; -3.843 ns ; jin  ; y2      ; clk      ;
; N/A           ; None        ; -3.843 ns ; jin  ; g2      ; clk      ;
+---------------+-------------+-----------+------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Jun 01 16:23:39 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jiao_tong -c jiao_tong --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk1khz" as buffer
    Info: Detected ripple clock "clk1hz" as buffer
Info: Clock "clk" has Internal fmax of 237.64 MHz between source register "stx.st1" and destination register "qh[1]" (period= 4.208 ns)
    Info: + Longest register to register delay is 3.944 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y11_N5; Fanout = 5; REG Node = 'stx.st1'
        Info: 2: + IC(0.455 ns) + CELL(0.366 ns) = 0.821 ns; Loc. = LCCOMB_X14_Y11_N6; Fanout = 2; COMB Node = 'qh[1]~488'
        Info: 3: + IC(0.703 ns) + CELL(0.647 ns) = 2.171 ns; Loc. = LCCOMB_X13_Y11_N28; Fanout = 1; COMB Node = 'qh[1]~489'
        Info: 4: + IC(0.382 ns) + CELL(0.206 ns) = 2.759 ns; Loc. = LCCOMB_X13_Y11_N6; Fanout = 3; COMB Node = 'qh[1]~490'
        Info: 5: + IC(0.330 ns) + CELL(0.855 ns) = 3.944 ns; Loc. = LCFF_X13_Y11_N11; Fanout = 5; REG Node = 'qh[1]'
        Info: Total cell delay = 2.074 ns ( 52.59 % )
        Info: Total interconnect delay = 1.870 ns ( 47.41 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 6.330 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.532 ns) + CELL(0.970 ns) = 2.592 ns; Loc. = LCFF_X1_Y9_N9; Fanout = 2; REG Node = 'clk1khz'
            Info: 3: + IC(0.386 ns) + CELL(0.970 ns) = 3.948 ns; Loc. = LCFF_X1_Y9_N27; Fanout = 15; REG Node = 'clk1hz'
            Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.771 ns; Loc. = CLKCTRL_G1; Fanout = 18; COMB Node = 'clk1hz~clkctrl'
            Info: 5: + IC(0.893 ns) + CELL(0.666 ns) = 6.330 ns; Loc. = LCFF_X13_Y11_N11; Fanout = 5; REG Node = 'qh[1]'
            Info: Total cell delay = 3.696 ns ( 58.39 % )
            Info: Total interconnect delay = 2.634 ns ( 41.61 % )
        Info: - Longest clock path from clock "clk" to source register is 6.330 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.532 ns) + CELL(0.970 ns) = 2.592 ns; Loc. = LCFF_X1_Y9_N9; Fanout = 2; REG Node = 'clk1khz'
            Info: 3: + IC(0.386 ns) + CELL(0.970 ns) = 3.948 ns; Loc. = LCFF_X1_Y9_N27; Fanout = 15; REG Node = 'clk1hz'
            Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.771 ns; Loc. = CLKCTRL_G1; Fanout = 18; COMB Node = 'clk1hz~clkctrl'
            Info: 5: + IC(0.893 ns) + CELL(0.666 ns) = 6.330 ns; Loc. = LCFF_X14_Y11_N5; Fanout = 5; REG Node = 'stx.st1'
            Info: Total cell delay = 3.696 ns ( 58.39 % )
            Info: Total interconnect delay = 2.634 ns ( 41.61 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "r1" (data pin = "jin", clock pin = "clk") is 4.109 ns
    Info: + Longest pin to register delay is 10.474 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_63; Fanout = 25; PIN Node = 'jin'
        Info: 2: + IC(7.811 ns) + CELL(0.537 ns) = 9.292 ns; Loc. = LCCOMB_X10_Y11_N12; Fanout = 5; COMB Node = 'r1~47'
        Info: 3: + IC(0.327 ns) + CELL(0.855 ns) = 10.474 ns; Loc. = LCFF_X10_Y11_N11; Fanout = 2; REG Node = 'r1'
        Info: Total cell delay = 2.336 ns ( 22.30 % )
        Info: Total interconnect delay = 8.138 ns ( 77.70 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 6.325 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.532 ns) + CELL(0.970 ns) = 2.592 ns; Loc. = LCFF_X1_Y9_N9; Fanout = 2; REG Node = 'clk1khz'
        Info: 3: + IC(0.386 ns) + CELL(0.970 ns) = 3.948 ns; Loc. = LCFF_X1_Y9_N27; Fanout = 15; REG Node = 'clk1hz'
        Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.771 ns; Loc. = CLKCTRL_G1; Fanout = 18; COMB Node = 'clk1hz~clkctrl'
        Info: 5: + IC(0.888 ns) + CELL(0.666 ns) = 6.325 ns; Loc. = LCFF_X10_Y11_N11; Fanout = 2; REG Node = 'r1'
        Info: Total cell delay = 3.696 ns ( 58.43 % )
        Info: Total interconnect delay = 2.629 ns ( 41.57 % )
Info: tco from clock "clk" to destination pin "seg7[4]" through register "qh[1]" is 16.748 ns
    Info: + Longest clock path from clock "clk" to source register is 6.330 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.532 ns) + CELL(0.970 ns) = 2.592 ns; Loc. = LCFF_X1_Y9_N9; Fanout = 2; REG Node = 'clk1khz'
        Info: 3: + IC(0.386 ns) + CELL(0.970 ns) = 3.948 ns; Loc. = LCFF_X1_Y9_N27; Fanout = 15; REG Node = 'clk1hz'
        Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.771 ns; Loc. = CLKCTRL_G1; Fanout = 18; COMB Node = 'clk1hz~clkctrl'
        Info: 5: + IC(0.893 ns) + CELL(0.666 ns) = 6.330 ns; Loc. = LCFF_X13_Y11_N11; Fanout = 5; REG Node = 'qh[1]'
        Info: Total cell delay = 3.696 ns ( 58.39 % )
        Info: Total interconnect delay = 2.634 ns ( 41.61 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 10.114 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y11_N11; Fanout = 5; REG Node = 'qh[1]'
        Info: 2: + IC(1.882 ns) + CELL(0.370 ns) = 2.252 ns; Loc. = LCCOMB_X12_Y11_N6; Fanout = 7; COMB Node = 'Mux11~14'
        Info: 3: + IC(1.067 ns) + CELL(0.624 ns) = 3.943 ns; Loc. = LCCOMB_X14_Y11_N24; Fanout = 1; COMB Node = 'Mux6~23'
        Info: 4: + IC(0.676 ns) + CELL(0.202 ns) = 4.821 ns; Loc. = LCCOMB_X14_Y11_N8; Fanout = 1; COMB Node = 'seg7~249'
        Info: 5: + IC(2.067 ns) + CELL(3.226 ns) = 10.114 ns; Loc. = PIN_125; Fanout = 0; PIN Node = 'seg7[4]'
        Info: Total cell delay = 4.422 ns ( 43.72 % )
        Info: Total interconnect delay = 5.692 ns ( 56.28 % )
Info: Longest tpd from source pin "jin" to destination pin "seg7[4]" is 14.352 ns
    Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_63; Fanout = 25; PIN Node = 'jin'
    Info: 2: + IC(7.745 ns) + CELL(0.370 ns) = 9.059 ns; Loc. = LCCOMB_X14_Y11_N8; Fanout = 1; COMB Node = 'seg7~249'
    Info: 3: + IC(2.067 ns) + CELL(3.226 ns) = 14.352 ns; Loc. = PIN_125; Fanout = 0; PIN Node = 'seg7[4]'
    Info: Total cell delay = 4.540 ns ( 31.63 % )
    Info: Total interconnect delay = 9.812 ns ( 68.37 % )
Info: th for register "ql[2]" (data pin = "jin", clock pin = "clk") is -2.463 ns
    Info: + Longest clock path from clock "clk" to destination register is 6.330 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.532 ns) + CELL(0.970 ns) = 2.592 ns; Loc. = LCFF_X1_Y9_N9; Fanout = 2; REG Node = 'clk1khz'
        Info: 3: + IC(0.386 ns) + CELL(0.970 ns) = 3.948 ns; Loc. = LCFF_X1_Y9_N27; Fanout = 15; REG Node = 'clk1hz'
        Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.771 ns; Loc. = CLKCTRL_G1; Fanout = 18; COMB Node = 'clk1hz~clkctrl'
        Info: 5: + IC(0.893 ns) + CELL(0.666 ns) = 6.330 ns; Loc. = LCFF_X13_Y11_N13; Fanout = 5; REG Node = 'ql[2]'
        Info: Total cell delay = 3.696 ns ( 58.39 % )
        Info: Total interconnect delay = 2.634 ns ( 41.61 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 9.099 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_63; Fanout = 25; PIN Node = 'jin'
        Info: 2: + IC(7.300 ns) + CELL(0.855 ns) = 9.099 ns; Loc. = LCFF_X13_Y11_N13; Fanout = 5; REG Node = 'ql[2]'
        Info: Total cell delay = 1.799 ns ( 19.77 % )
        Info: Total interconnect delay = 7.300 ns ( 80.23 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Fri Jun 01 16:23:42 2007
    Info: Elapsed time: 00:00:03