jiao_tong.rpt

在quartus开发环境下

  _EQ080 =  _LC2_A8 &  stx0
         #  _LC6_A3;

-- Node name is '~2254~4' 
-- Equation name is '~2254~4', location is LC3_A3, type is buried.
-- synthesized logic cell 
_LC3_A3  = LCELL( _EQ081);
  _EQ081 =  _LC2_A3 &  qh0 &  qh1
         #  _LC2_A3 & !_LC5_A6 &  qh1
         #  _LC2_A3 &  _LC5_A6 & !qh0 & !qh1;

-- Node name is '~2254~5' 
-- Equation name is '~2254~5', location is LC5_A3, type is buried.
-- synthesized logic cell 
_LC5_A3  = LCELL( _EQ082);
  _EQ082 =  _LC1_A7 & !_LC1_A13
         # !_LC1_A13 & !stx0 &  stx1;

-- Node name is '~2266~1' 
-- Equation name is '~2266~1', location is LC1_A9, type is buried.
-- synthesized logic cell 
_LC1_A9  = LCELL( _EQ083);
  _EQ083 = !jin &  _LC5_A6 & !qh0
         # !_LC1_A7 &  _LC5_A6 & !qh0
         # !_LC5_A6 &  qh0;

-- Node name is '~2266~2' 
-- Equation name is '~2266~2', location is LC2_A9, type is buried.
-- synthesized logic cell 
_LC2_A9  = LCELL( _EQ084);
  _EQ084 = !_LC1_A7 &  _LC1_A9 &  _LC2_A8
         # !_LC1_A5 &  _LC1_A7 &  _LC1_A9;

-- Node name is '~2290~1' 
-- Equation name is '~2290~1', location is LC3_A6, type is buried.
-- synthesized logic cell 
_LC3_A6  = LCELL( _EQ085);
  _EQ085 = !_LC1_A5 & !_LC4_A6 &  ql3
         # !a;

-- Node name is '~2350~1' 
-- Equation name is '~2350~1', location is LC2_A4, type is buried.
-- synthesized logic cell 
_LC2_A4  = LCELL( _EQ086);
  _EQ086 =  jin
         # !a
         # !_LC1_A5;

-- Node name is '~2350~2' 
-- Equation name is '~2350~2', location is LC3_A4, type is buried.
-- synthesized logic cell 
_LC3_A4  = LCELL( _EQ087);
  _EQ087 =  _LC5_A4 &  stx0 & !stx1
         #  _LC2_A4 &  stx0 &  stx1;

-- Node name is ':3020' 
-- Equation name is '_LC1_B8', type is buried 
_LC1_B8  = LCELL( _EQ088);
  _EQ088 =  r1
         #  jin;

-- Node name is ':3026' 
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = LCELL( _EQ089);
  _EQ089 =  jin
         #  r2;

-- Node name is ':3034' 
-- Equation name is '_LC1_B6', type is buried 
_LC1_B6  = LCELL( _EQ090);
  _EQ090 =  g1 & !jin;

-- Node name is ':3040' 
-- Equation name is '_LC1_A3', type is buried 
_LC1_A3  = LCELL( _EQ091);
  _EQ091 =  g2 & !jin;

-- Node name is ':3046' 
-- Equation name is '_LC1_B7', type is buried 
_LC1_B7  = LCELL( _EQ092);
  _EQ092 = !jin &  y1;

-- Node name is ':3052' 
-- Equation name is '_LC1_A4', type is buried 
_LC1_A4  = LCELL( _EQ093);
  _EQ093 = !jin &  y2;

-- Node name is '~3056~1' 
-- Equation name is '~3056~1', location is LC4_B5, type is buried.
-- synthesized logic cell 
_LC4_B5  = LCELL( _EQ094);
  _EQ094 = !jin
         #  clk1hz;

-- Node name is ':3056' 
-- Equation name is '_LC4_B13', type is buried 
_LC4_B13 = LCELL( _EQ095);
  _EQ095 = !jin &  _LC5_A1
         # !jin &  _LC2_A1
         #  clk1hz &  _LC5_A1
         #  clk1hz &  _LC2_A1;

-- Node name is ':3062' 
-- Equation name is '_LC4_B7', type is buried 
_LC4_B7  = LCELL( _EQ096);
  _EQ096 = !jin &  _LC2_B7
         #  clk1hz &  _LC2_B7
         # !jin & !_LC5_A13
         #  clk1hz & !_LC5_A13;

-- Node name is ':3068' 
-- Equation name is '_LC2_B4', type is buried 
_LC2_B4  = LCELL( _EQ097);
  _EQ097 = !jin &  _LC4_A10
         #  clk1hz &  _LC4_A10;

-- Node name is ':3074' 
-- Equation name is '_LC3_B4', type is buried 
_LC3_B4  = LCELL( _EQ098);
  _EQ098 = !jin &  _LC5_A2
         #  clk1hz &  _LC5_A2;

-- Node name is ':3080' 
-- Equation name is '_LC1_B5', type is buried 
_LC1_B5  = LCELL( _EQ099);
  _EQ099 = !_LC1_A1 &  _LC1_A8 &  _LC4_B5
         #  _LC2_A1 &  _LC4_B5;

-- Node name is ':3086' 
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = LCELL( _EQ100);
  _EQ100 =  _LC4_B5 &  _LC6_B5
         #  _LC2_A1 &  _LC4_B5;

-- Node name is ':3092' 
-- Equation name is '_LC3_B5', type is buried 
_LC3_B5  = LCELL( _EQ101);
  _EQ101 = !_LC1_A1 & !_LC2_A1 & !_LC2_A10 &  _LC4_B5;

-- Node name is ':3262' 
-- Equation name is '_LC2_A5', type is buried 
_LC2_A5  = LCELL( _EQ102);
  _EQ102 =  _LC3_A5
         # !cnt0 & !cnt1 &  ql3;

-- Node name is ':3264' 
-- Equation name is '_LC3_A5', type is buried 
_LC3_A5  = LCELL( _EQ103);
  _EQ103 =  cnt1 &  _LC2_A5
         #  cnt0 & !cnt1 &  qh3;

-- Node name is ':3271' 
-- Equation name is '_LC2_A11', type is buried 
_LC2_A11 = LCELL( _EQ104);
  _EQ104 =  _LC3_A11
         # !cnt0 & !cnt1 &  ql2;

-- Node name is ':3273' 
-- Equation name is '_LC3_A11', type is buried 
_LC3_A11 = LCELL( _EQ105);
  _EQ105 =  cnt1 &  _LC2_A11
         #  cnt0 & !cnt1 &  qh2;

-- Node name is ':3280' 
-- Equation name is '_LC2_A12', type is buried 
_LC2_A12 = LCELL( _EQ106);
  _EQ106 =  _LC3_A12
         # !cnt0 & !cnt1 &  ql1;

-- Node name is ':3282' 
-- Equation name is '_LC3_A12', type is buried 
_LC3_A12 = LCELL( _EQ107);
  _EQ107 =  cnt0 & !cnt1 &  qh1
         #  cnt1 &  _LC2_A12;

-- Node name is ':3289' 
-- Equation name is '_LC4_A12', type is buried 
_LC4_A12 = LCELL( _EQ108);
  _EQ108 =  _LC5_A12
         # !cnt0 & !cnt1 &  ql0;

-- Node name is ':3291' 
-- Equation name is '_LC5_A12', type is buried 
_LC5_A12 = LCELL( _EQ109);
  _EQ109 =  cnt1 &  _LC4_A12
         #  cnt0 & !cnt1 &  qh0;

-- Node name is ':3298' 
-- Equation name is '_LC1_A12', type is buried 
_LC1_A12 = LCELL( _EQ110);
  _EQ110 =  cnt0 & !cnt1
         #  cnt0 &  _LC1_A12
         #  cnt1 &  _LC1_A12;

-- Node name is ':3307' 
-- Equation name is '_LC1_A11', type is buried 
_LC1_A11 = LCELL( _EQ111);
  _EQ111 = !cnt0 & !cnt1
         # !cnt0 &  _LC1_A11
         #  cnt1 &  _LC1_A11;

-- Node name is ':3594' 
-- Equation name is '_LC2_A10', type is buried 
!_LC2_A10 = _LC2_A10~NOT;
_LC2_A10~NOT = LCELL( _EQ112);
  _EQ112 =  _LC2_A5
         # !_LC2_A12
         # !_LC4_A12
         # !_LC2_A11;

-- Node name is ':3666' 
-- Equation name is '_LC1_A1', type is buried 
!_LC1_A1 = _LC1_A1~NOT;
_LC1_A1~NOT = LCELL( _EQ113);
  _EQ113 =  _LC2_A11
         #  _LC2_A12
         # !_LC4_A12
         #  _LC2_A5;

-- Node name is ':3678' 
-- Equation name is '_LC2_A1', type is buried 
!_LC2_A1 = _LC2_A1~NOT;
_LC2_A1~NOT = LCELL( _EQ114);
  _EQ114 =  _LC2_A11
         #  _LC2_A12
         #  _LC4_A12
         #  _LC2_A5;

-- Node name is ':3683' 
-- Equation name is '_LC5_A1', type is buried 
!_LC5_A1 = _LC5_A1~NOT;
_LC5_A1~NOT = LCELL( _EQ115);
  _EQ115 = !_LC2_A5 &  _LC2_A11 & !_LC2_A12 & !_LC4_A12
         # !_LC2_A5 & !_LC2_A11 & !_LC2_A12 &  _LC4_A12;

-- Node name is ':3704' 
-- Equation name is '_LC4_A2', type is buried 
_LC4_A2  = LCELL( _EQ116);
  _EQ116 =  _LC2_A5 & !_LC2_A11 & !_LC2_A12
         # !_LC2_A5 &  _LC2_A11 &  _LC2_A12 &  _LC4_A12;

-- Node name is '~3714~1' 
-- Equation name is '~3714~1', location is LC2_B7, type is buried.
-- synthesized logic cell 
_LC2_B7  = LCELL( _EQ117);
  _EQ117 = !_LC5_A1
         #  _LC4_A2
         #  _LC2_A1;

-- Node name is ':3747' 
-- Equation name is '_LC4_A10', type is buried 
_LC4_A10 = LCELL( _EQ118);
  _EQ118 = !_LC2_A5 &  _LC2_A11
         # !_LC2_A5 &  _LC2_A12 &  _LC4_A12
         # !_LC2_A11 & !_LC2_A12;

-- Node name is ':3780' 
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = LCELL( _EQ119);
  _EQ119 =  _LC2_A5
         #  _LC2_A12 & !_LC4_A12
         # !_LC2_A11 &  _LC2_A12
         # !_LC2_A11 & !_LC4_A12
         #  _LC2_A11 & !_LC2_A12 &  _LC4_A12;

-- Node name is ':3807' 
-- Equation name is '_LC1_A8', type is buried 
_LC1_A8  = LCELL( _EQ120);
  _EQ120 =  _LC2_A5 &  _LC2_A11
         #  _LC2_A5 &  _LC2_A12
         #  _LC2_A5 & !_LC4_A12
         #  _LC2_A12 & !_LC4_A12
         # !_LC2_A11 & !_LC4_A12
         # !_LC2_A5 & !_LC2_A11 & !_LC2_A12;

-- Node name is '~3848~1' 
-- Equation name is '~3848~1', location is LC5_A13, type is buried.
-- synthesized logic cell 
_LC5_A13 = LCELL( _EQ121);
  _EQ121 =  _LC2_A5
         # !_LC2_A12
         #  _LC2_A11;

-- Node name is ':3848' 
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = LCELL( _EQ122);
  _EQ122 = !_LC1_A1 & !_LC2_A10 &  _LC5_A13;



Project Information                 g:\eda_2\jiao_tong\jiao_tong\jiao_tong.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX8000' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 9,787K