📄 dds.tan.qmsg
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{ "Info" "ITDB_TSU_RESULT" "SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\] Pword\[1\] clock 3.485 ns register " "Info: tsu for register \"SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\]\" (data pin = \"Pword\[1\]\", clock pin = \"clock\") is 3.485 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.508 ns + Longest pin register " "Info: + Longest pin to register delay is 6.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns Pword\[1\] 1 PIN PIN_G22 3 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G22; Fanout = 3; PIN Node = 'Pword\[1\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Pword[1] } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/my_eda3/DDS/DDS.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.164 ns) + CELL(0.344 ns) 5.742 ns SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[1\]~29 2 COMB LC_X17_Y18_N2 2 " "Info: 2: + IC(4.164 ns) + CELL(0.344 ns) = 5.742 ns; Loc. = LC_X17_Y18_N2; Fanout = 2; COMB Node = 'SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[1\]~29'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.508 ns" { Pword[1] SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~29 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 5.800 ns SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[2\]~30 3 COMB LC_X17_Y18_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 5.800 ns; Loc. = LC_X17_Y18_N3; Fanout = 2; COMB Node = 'SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[2\]~30'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~29 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~30 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.130 ns) 5.930 ns SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~31 4 COMB LC_X17_Y18_N4 3 " "Info: 4: + IC(0.000 ns) + CELL(0.130 ns) = 5.930 ns; Loc. = LC_X17_Y18_N4; Fanout = 3; COMB Node = 'SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~31'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.130 ns" { SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~30 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~31 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.578 ns) 6.508 ns SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\] 5 REG LC_X17_Y18_N5 3 " "Info: 5: + IC(0.000 ns) + CELL(0.578 ns) = 6.508 ns; Loc. = LC_X17_Y18_N5; Fanout = 3; REG Node = 'SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.578 ns" { SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~31 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.344 ns ( 36.02 % ) " "Info: Total cell delay = 2.344 ns ( 36.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.164 ns ( 63.98 % ) " "Info: Total interconnect delay = 4.164 ns ( 63.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.508 ns" { Pword[1] SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~29 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~30 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~31 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.508 ns" { Pword[1] Pword[1]~out0 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~29 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~30 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~31 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } { 0.000ns 0.000ns 4.164ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.234ns 0.344ns 0.058ns 0.130ns 0.578ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.033 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 3.033 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/my_eda3/DDS/DDS.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.663 ns) + CELL(0.542 ns) 3.033 ns SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\] 2 REG LC_X17_Y18_N5 3 " "Info: 2: + IC(1.663 ns) + CELL(0.542 ns) = 3.033 ns; Loc. = LC_X17_Y18_N5; Fanout = 3; REG Node = 'SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.205 ns" { clock SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.17 % ) " "Info: Total cell delay = 1.370 ns ( 45.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.663 ns ( 54.83 % ) " "Info: Total interconnect delay = 1.663 ns ( 54.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { clock SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { clock clock~out0 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.508 ns" { Pword[1] SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~29 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~30 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~31 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.508 ns" { Pword[1] Pword[1]~out0 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~29 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~30 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~31 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } { 0.000ns 0.000ns 4.164ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.234ns 0.344ns 0.058ns 0.130ns 0.578ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { clock SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { clock clock~out0 SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock Sout\[7\] AltiMult:Producti\|resdtb\[16\] 7.301 ns register " "Info: tco from clock \"clock\" to destination pin \"Sout\[7\]\" through register \"AltiMult:Producti\|resdtb\[16\]\" is 7.301 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.061 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/my_eda3/DDS/DDS.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.691 ns) + CELL(0.542 ns) 3.061 ns AltiMult:Producti\|resdtb\[16\] 2 REG LC_X12_Y15_N2 1 " "Info: 2: + IC(1.691 ns) + CELL(0.542 ns) = 3.061 ns; Loc. = LC_X12_Y15_N2; Fanout = 1; REG Node = 'AltiMult:Producti\|resdtb\[16\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.233 ns" { clock AltiMult:Producti|resdtb[16] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.76 % ) " "Info: Total cell delay = 1.370 ns ( 44.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.691 ns ( 55.24 % ) " "Info: Total interconnect delay = 1.691 ns ( 55.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.061 ns" { clock AltiMult:Producti|resdtb[16] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.061 ns" { clock clock~out0 AltiMult:Producti|resdtb[16] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.084 ns + Longest register pin " "Info: + Longest register to pin delay is 4.084 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AltiMult:Producti\|resdtb\[16\] 1 REG LC_X12_Y15_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y15_N2; Fanout = 1; REG Node = 'AltiMult:Producti\|resdtb\[16\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { AltiMult:Producti|resdtb[16] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.708 ns) + CELL(2.376 ns) 4.084 ns Sout\[7\] 2 PIN PIN_P20 0 " "Info: 2: + IC(1.708 ns) + CELL(2.376 ns) = 4.084 ns; Loc. = PIN_P20; Fanout = 0; PIN Node = 'Sout\[7\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.084 ns" { AltiMult:Producti|resdtb[16] Sout[7] } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/my_eda3/DDS/DDS.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns ( 58.18 % ) " "Info: Total cell delay = 2.376 ns ( 58.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.708 ns ( 41.82 % ) " "Info: Total interconnect delay = 1.708 ns ( 41.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.084 ns" { AltiMult:Producti|resdtb[16] Sout[7] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.084 ns" { AltiMult:Producti|resdtb[16] Sout[7] } { 0.000ns 1.708ns } { 0.000ns 2.376ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.061 ns" { clock AltiMult:Producti|resdtb[16] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.061 ns" { clock clock~out0 AltiMult:Producti|resdtb[16] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.084 ns" { AltiMult:Producti|resdtb[16] Sout[7] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.084 ns" { AltiMult:Producti|resdtb[16] Sout[7] } { 0.000ns 1.708ns } { 0.000ns 2.376ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "SDelay:Delayi\|result\[2\] sclrp clock 0.162 ns register " "Info: th for register \"SDelay:Delayi\|result\[2\]\" (data pin = \"sclrp\", clock pin = \"clock\") is 0.162 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.959 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/my_eda3/DDS/DDS.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.589 ns) + CELL(0.542 ns) 2.959 ns SDelay:Delayi\|result\[2\] 2 REG LC_X3_Y21_N2 3 " "Info: 2: + IC(1.589 ns) + CELL(0.542 ns) = 2.959 ns; Loc. = LC_X3_Y21_N2; Fanout = 3; REG Node = 'SDelay:Delayi\|result\[2\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.131 ns" { clock SDelay:Delayi|result[2] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.30 % ) " "Info: Total cell delay = 1.370 ns ( 46.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.589 ns ( 53.70 % ) " "Info: Total interconnect delay = 1.589 ns ( 53.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.959 ns" { clock SDelay:Delayi|result[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.959 ns" { clock clock~out0 SDelay:Delayi|result[2] } { 0.000ns 0.000ns 1.589ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.897 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns sclrp 1 PIN PIN_M21 97 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 97; PIN Node = 'sclrp'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclrp } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/my_eda3/DDS/DDS.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.949 ns) + CELL(0.223 ns) 2.897 ns SDelay:Delayi\|result\[2\] 2 REG LC_X3_Y21_N2 3 " "Info: 2: + IC(1.949 ns) + CELL(0.223 ns) = 2.897 ns; Loc. = LC_X3_Y21_N2; Fanout = 3; REG Node = 'SDelay:Delayi\|result\[2\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.172 ns" { sclrp SDelay:Delayi|result[2] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.948 ns ( 32.72 % ) " "Info: Total cell delay = 0.948 ns ( 32.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.949 ns ( 67.28 % ) " "Info: Total interconnect delay = 1.949 ns ( 67.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { sclrp SDelay:Delayi|result[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { sclrp sclrp~out0 SDelay:Delayi|result[2] } { 0.000ns 0.000ns 1.949ns } { 0.000ns 0.725ns 0.223ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.959 ns" { clock SDelay:Delayi|result[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.959 ns" { clock clock~out0 SDelay:Delayi|result[2] } { 0.000ns 0.000ns 1.589ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { sclrp SDelay:Delayi|result[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { sclrp sclrp~out0 SDelay:Delayi|result[2] } { 0.000ns 0.000ns 1.949ns } { 0.000ns 0.725ns 0.223ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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