dds.tan.qmsg

在quartus开发环境下

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "DDS.vhd" "" { Text "D:/my_eda3/DDS/DDS.vhd" 34 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clock memory altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|ram_block1a1~porta_address_reg9 register AltiMult:Producti\|resdtb\[12\] 8.679 ns " "Info: Slack time is 8.679 ns for clock \"clock\" between source memory \"altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|ram_block1a1~porta_address_reg9\" and destination register \"AltiMult:Producti\|resdtb\[12\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "88.33 MHz 11.321 ns " "Info: Fmax is 88.33 MHz (period= 11.321 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.620 ns + Largest memory register " "Info: + Largest memory to register requirement is 19.620 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.050 ns + Largest " "Info: + Largest clock skew is 0.050 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.053 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.053 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/my_eda3/DDS/DDS.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.683 ns) + CELL(0.542 ns) 3.053 ns AltiMult:Producti\|resdtb\[12\] 2 REG LC_X8_Y14_N2 1 " "Info: 2: + IC(1.683 ns) + CELL(0.542 ns) = 3.053 ns; Loc. = LC_X8_Y14_N2; Fanout = 1; REG Node = 'AltiMult:Producti\|resdtb\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.225 ns" { clock AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.87 % ) " "Info: Total cell delay = 1.370 ns ( 44.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.683 ns ( 55.13 % ) " "Info: Total interconnect delay = 1.683 ns ( 55.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.053 ns" { clock AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.053 ns" { clock clock~out0 AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.683ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.003 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 3.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/my_eda3/DDS/DDS.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.663 ns) + CELL(0.512 ns) 3.003 ns altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|ram_block1a1~porta_address_reg9 2 MEM M4K_X15_Y18 2 " "Info: 2: + IC(1.663 ns) + CELL(0.512 ns) = 3.003 ns; Loc. = M4K_X15_Y18; Fanout = 2; MEM Node = 'altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|ram_block1a1~porta_address_reg9'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.175 ns" { clock altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_p5u.tdf" "" { Text "D:/my_eda3/DDS/db/altsyncram_p5u.tdf" 61 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.340 ns ( 44.62 % ) " "Info: Total cell delay = 1.340 ns ( 44.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.663 ns ( 55.38 % ) " "Info: Total interconnect delay = 1.663 ns ( 55.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.003 ns" { clock altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.003 ns" { clock clock~out0 altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.512ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.053 ns" { clock AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.053 ns" { clock clock~out0 AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.683ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.003 ns" { clock altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.003 ns" { clock clock~out0 altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.512ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns - " "Info: - Micro clock to output delay of source is 0.420 ns" {  } { { "db/altsyncram_p5u.tdf" "" { Text "D:/my_eda3/DDS/db/altsyncram_p5u.tdf" 61 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.053 ns" { clock AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.053 ns" { clock clock~out0 AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.683ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.003 ns" { clock altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.003 ns" { clock clock~out0 altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.512ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.941 ns - Longest memory register " "Info: - Longest memory to register delay is 10.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|ram_block1a1~porta_address_reg9 1 MEM M4K_X15_Y18 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X15_Y18; Fanout = 2; MEM Node = 'altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|ram_block1a1~porta_address_reg9'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_p5u.tdf" "" { Text "D:/my_eda3/DDS/db/altsyncram_p5u.tdf" 61 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.069 ns) 3.069 ns altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|q_a\[0\] 2 MEM M4K_X15_Y18 1 " "Info: 2: + IC(0.000 ns) + CELL(3.069 ns) = 3.069 ns; Loc. = M4K_X15_Y18; Fanout = 1; MEM Node = 'altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|q_a\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.069 ns" { altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_p5u.tdf" "" { Text "D:/my_eda3/DDS/db/altsyncram_p5u.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.176 ns) + CELL(0.075 ns) 4.320 ns AltiMult:Producti\|dataaint~212 3 COMB LC_X13_Y16_N2 22 " "Info: 3: + IC(1.176 ns) + CELL(0.075 ns) = 4.320 ns; Loc. = LC_X13_Y16_N2; Fanout = 22; COMB Node = 'AltiMult:Producti\|dataaint~212'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.251 ns" { altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|q_a[0] AltiMult:Producti|dataaint~212 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1622 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.853 ns) + CELL(3.451 ns) 8.624 ns AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|mac_mult2~DATAOUT21 4 COMB DSPMULT_X10_Y15_N0 10 " "Info: 4: + IC(0.853 ns) + CELL(3.451 ns) = 8.624 ns; Loc. = DSPMULT_X10_Y15_N0; Fanout = 10; COMB Node = 'AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|mac_mult2~DATAOUT21'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.304 ns" { AltiMult:Producti|dataaint~212 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 } "NODE_NAME" } } { "db/mult_6h01.tdf" "" { Text "D:/my_eda3/DDS/db/mult_6h01.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.878 ns) 9.502 ns AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|result\[12\] 5 COMB DSPOUT_X11_Y9_N0 1 " "Info: 5: + IC(0.000 ns) + CELL(0.878 ns) = 9.502 ns; Loc. = DSPOUT_X11_Y9_N0; Fanout = 1; COMB Node = 'AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|result\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.878 ns" { AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] } "NODE_NAME" } } { "db/mult_6h01.tdf" "" { Text "D:/my_eda3/DDS/db/mult_6h01.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.120 ns) + CELL(0.319 ns) 10.941 ns AltiMult:Producti\|resdtb\[12\] 6 REG LC_X8_Y14_N2 1 " "Info: 6: + IC(1.120 ns) + CELL(0.319 ns) = 10.941 ns; Loc. = LC_X8_Y14_N2; Fanout = 1; REG Node = 'AltiMult:Producti\|resdtb\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.439 ns" { AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.792 ns ( 71.22 % ) " "Info: Total cell delay = 7.792 ns ( 71.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.149 ns ( 28.78 % ) " "Info: Total interconnect delay = 3.149 ns ( 28.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.941 ns" { altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|q_a[0] AltiMult:Producti|dataaint~212 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.941 ns" { altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|q_a[0] AltiMult:Producti|dataaint~212 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.176ns 0.853ns 0.000ns 1.120ns } { 0.000ns 3.069ns 0.075ns 3.451ns 0.878ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.053 ns" { clock AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.053 ns" { clock clock~out0 AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.683ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.003 ns" { clock altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.003 ns" { clock clock~out0 altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.512ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.941 ns" { altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|q_a[0] AltiMult:Producti|dataaint~212 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.941 ns" { altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|q_a[0] AltiMult:Producti|dataaint~212 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.176ns 0.853ns 0.000ns 1.120ns } { 0.000ns 3.069ns 0.075ns 3.451ns 0.878ns 0.319ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock register SDelay:Delayi\|result\[29\] register SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[12\] 888 ps " "Info: Minimum slack time is 888 ps for clock \"clock\" between source register \"SDelay:Delayi\|result\[29\]\" and destination register \"SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[12\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.832 ns + Shortest register register " "Info: + Shortest register to register delay is 0.832 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDelay:Delayi\|result\[29\] 1 REG LC_X18_Y18_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y18_N9; Fanout = 3; REG Node = 'SDelay:Delayi\|result\[29\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDelay:Delayi|result[29] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.374 ns) + CELL(0.458 ns) 0.832 ns SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[12\] 2 REG LC_X18_Y18_N5 3 " "Info: 2: + IC(0.374 ns) + CELL(0.458 ns) = 0.832 ns; Loc. = LC_X18_Y18_N5; Fanout = 3; REG Node = 'SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.832 ns" { SDelay:Delayi|result[29] SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.458 ns ( 55.05 % ) " "Info: Total cell delay = 0.458 ns ( 55.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.374 ns ( 44.95 % ) " "Info: Total interconnect delay = 0.374 ns ( 44.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.832 ns" { SDelay:Delayi|result[29] SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.832 ns" { SDelay:Delayi|result[29] SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.374ns } { 0.000ns 0.458ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.056 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.056 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.033 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 3.033 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/my_eda3/DDS/DDS.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.663 ns) + CELL(0.542 ns) 3.033 ns SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[12\] 2 REG LC_X18_Y18_N5 3 " "Info: 2: + IC(1.663 ns) + CELL(0.542 ns) = 3.033 ns; Loc. = LC_X18_Y18_N5; Fanout = 3; REG Node = 'SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.205 ns" { clock SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.17 % ) " "Info: Total cell delay = 1.370 ns ( 45.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.663 ns ( 54.83 % ) " "Info: Total interconnect delay = 1.663 ns ( 54.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { clock SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { clock clock~out0 SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.033 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to source register is 3.033 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/my_eda3/DDS/DDS.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.663 ns) + CELL(0.542 ns) 3.033 ns SDelay:Delayi\|result\[29\] 2 REG LC_X18_Y18_N9 3 " "Info: 2: + IC(1.663 ns) + CELL(0.542 ns) = 3.033 ns; Loc. = LC_X18_Y18_N9; Fanout = 3; REG Node = 'SDelay:Delayi\|result\[29\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.205 ns" { clock SDelay:Delayi|result[29] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.17 % ) " "Info: Total cell delay = 1.370 ns ( 45.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.663 ns ( 54.83 % ) " "Info: Total interconnect delay = 1.663 ns ( 54.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { clock SDelay:Delayi|result[29] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { clock clock~out0 SDelay:Delayi|result[29] } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { clock SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { clock clock~out0 SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { clock SDelay:Delayi|result[29] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { clock clock~out0 SDelay:Delayi|result[29] } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns - " "Info: - Micro clock to output delay of source is 0.156 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { clock SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { clock clock~out0 SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { clock SDelay:Delayi|result[29] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { clock clock~out0 SDelay:Delayi|result[29] } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.832 ns" { SDelay:Delayi|result[29] SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.832 ns" { SDelay:Delayi|result[29] SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.374ns } { 0.000ns 0.458ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { clock SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { clock clock~out0 SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { clock SDelay:Delayi|result[29] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { clock clock~out0 SDelay:Delayi|result[29] } { 0.000ns 0.000ns 1.663ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}