dds_top.tan.qmsg

在quartus开发环境下

{ "Info" "ITDB_TSU_RESULT" "DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\] Pword\[4\] clock 3.306 ns register " "Info: tsu for register \"DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\]\" (data pin = \"Pword\[4\]\", clock pin = \"clock\") is 3.306 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.327 ns + Longest pin register " "Info: + Longest pin to register delay is 6.327 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns Pword\[4\] 1 PIN PIN_L15 3 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L15; Fanout = 3; PIN Node = 'Pword\[4\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Pword[4] } "NODE_NAME" } } { "dds_top.vhd" "" { Text "D:/my_eda3/DDS/dds_top.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.172 ns) + CELL(0.451 ns) 5.710 ns DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\]~16COUT1 2 COMB LC_X19_Y18_N6 2 " "Info: 2: + IC(4.172 ns) + CELL(0.451 ns) = 5.710 ns; Loc. = LC_X19_Y18_N6; Fanout = 2; COMB Node = 'DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\]~16COUT1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.623 ns" { Pword[4] DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~16COUT1 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 5.770 ns DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[1\]~17COUT1 3 COMB LC_X19_Y18_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 5.770 ns; Loc. = LC_X19_Y18_N7; Fanout = 2; COMB Node = 'DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[1\]~17COUT1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~16COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~17COUT1 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 5.830 ns DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[2\]~18COUT1 4 COMB LC_X19_Y18_N8 1 " "Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 5.830 ns; Loc. = LC_X19_Y18_N8; Fanout = 1; COMB Node = 'DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[2\]~18COUT1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~17COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~18COUT1 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.497 ns) 6.327 ns DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\] 5 REG LC_X19_Y18_N9 1 " "Info: 5: + IC(0.000 ns) + CELL(0.497 ns) = 6.327 ns; Loc. = LC_X19_Y18_N9; Fanout = 1; REG Node = 'DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.497 ns" { DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~18COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.155 ns ( 34.06 % ) " "Info: Total cell delay = 2.155 ns ( 34.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.172 ns ( 65.94 % ) " "Info: Total interconnect delay = 4.172 ns ( 65.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.327 ns" { Pword[4] DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~16COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~17COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~18COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.327 ns" { Pword[4] Pword[4]~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~16COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~17COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~18COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] } { 0.000ns 0.000ns 4.172ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.087ns 0.451ns 0.060ns 0.060ns 0.497ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.031 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 3.031 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dds_top.vhd" "" { Text "D:/my_eda3/DDS/dds_top.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.661 ns) + CELL(0.542 ns) 3.031 ns DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\] 2 REG LC_X19_Y18_N9 1 " "Info: 2: + IC(1.661 ns) + CELL(0.542 ns) = 3.031 ns; Loc. = LC_X19_Y18_N9; Fanout = 1; REG Node = 'DDS:DDSi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.203 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.20 % ) " "Info: Total cell delay = 1.370 ns ( 45.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.661 ns ( 54.80 % ) " "Info: Total interconnect delay = 1.661 ns ( 54.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.031 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.031 ns" { clock clock~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] } { 0.000ns 0.000ns 1.661ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.327 ns" { Pword[4] DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~16COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~17COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~18COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.327 ns" { Pword[4] Pword[4]~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~16COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~17COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~18COUT1 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] } { 0.000ns 0.000ns 4.172ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.087ns 0.451ns 0.060ns 0.060ns 0.497ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.031 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.031 ns" { clock clock~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] } { 0.000ns 0.000ns 1.661ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock Sout\[0\] DDS:DDSi\|AltiMult:Producti\|resdtb\[10\] 7.342 ns register " "Info: tco from clock \"clock\" to destination pin \"Sout\[0\]\" through register \"DDS:DDSi\|AltiMult:Producti\|resdtb\[10\]\" is 7.342 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.036 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.036 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dds_top.vhd" "" { Text "D:/my_eda3/DDS/dds_top.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.666 ns) + CELL(0.542 ns) 3.036 ns DDS:DDSi\|AltiMult:Producti\|resdtb\[10\] 2 REG LC_X41_Y16_N2 1 " "Info: 2: + IC(1.666 ns) + CELL(0.542 ns) = 3.036 ns; Loc. = LC_X41_Y16_N2; Fanout = 1; REG Node = 'DDS:DDSi\|AltiMult:Producti\|resdtb\[10\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.208 ns" { clock DDS:DDSi|AltiMult:Producti|resdtb[10] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.13 % ) " "Info: Total cell delay = 1.370 ns ( 45.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.666 ns ( 54.87 % ) " "Info: Total interconnect delay = 1.666 ns ( 54.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.036 ns" { clock DDS:DDSi|AltiMult:Producti|resdtb[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.036 ns" { clock clock~out0 DDS:DDSi|AltiMult:Producti|resdtb[10] } { 0.000ns 0.000ns 1.666ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.150 ns + Longest register pin " "Info: + Longest register to pin delay is 4.150 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DDS:DDSi\|AltiMult:Producti\|resdtb\[10\] 1 REG LC_X41_Y16_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y16_N2; Fanout = 1; REG Node = 'DDS:DDSi\|AltiMult:Producti\|resdtb\[10\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DDS:DDSi|AltiMult:Producti|resdtb[10] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.746 ns) + CELL(2.404 ns) 4.150 ns Sout\[0\] 2 PIN PIN_E8 0 " "Info: 2: + IC(1.746 ns) + CELL(2.404 ns) = 4.150 ns; Loc. = PIN_E8; Fanout = 0; PIN Node = 'Sout\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.150 ns" { DDS:DDSi|AltiMult:Producti|resdtb[10] Sout[0] } "NODE_NAME" } } { "dds_top.vhd" "" { Text "D:/my_eda3/DDS/dds_top.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 57.93 % ) " "Info: Total cell delay = 2.404 ns ( 57.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.746 ns ( 42.07 % ) " "Info: Total interconnect delay = 1.746 ns ( 42.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.150 ns" { DDS:DDSi|AltiMult:Producti|resdtb[10] Sout[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.150 ns" { DDS:DDSi|AltiMult:Producti|resdtb[10] Sout[0] } { 0.000ns 1.746ns } { 0.000ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.036 ns" { clock DDS:DDSi|AltiMult:Producti|resdtb[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.036 ns" { clock clock~out0 DDS:DDSi|AltiMult:Producti|resdtb[10] } { 0.000ns 0.000ns 1.666ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.150 ns" { DDS:DDSi|AltiMult:Producti|resdtb[10] Sout[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.150 ns" { DDS:DDSi|AltiMult:Producti|resdtb[10] Sout[0] } { 0.000ns 1.746ns } { 0.000ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "DDS:DDSi\|SDelay:Delayi\|result\[9\] sclrp clock 0.155 ns register " "Info: th for register \"DDS:DDSi\|SDelay:Delayi\|result\[9\]\" (data pin = \"sclrp\", clock pin = \"clock\") is 0.155 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.883 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.883 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dds_top.vhd" "" { Text "D:/my_eda3/DDS/dds_top.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.513 ns) + CELL(0.542 ns) 2.883 ns DDS:DDSi\|SDelay:Delayi\|result\[9\] 2 REG LC_X31_Y26_N2 3 " "Info: 2: + IC(1.513 ns) + CELL(0.542 ns) = 2.883 ns; Loc. = LC_X31_Y26_N2; Fanout = 3; REG Node = 'DDS:DDSi\|SDelay:Delayi\|result\[9\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.055 ns" { clock DDS:DDSi|SDelay:Delayi|result[9] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.52 % ) " "Info: Total cell delay = 1.370 ns ( 47.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.513 ns ( 52.48 % ) " "Info: Total interconnect delay = 1.513 ns ( 52.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.883 ns" { clock DDS:DDSi|SDelay:Delayi|result[9] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.883 ns" { clock clock~out0 DDS:DDSi|SDelay:Delayi|result[9] } { 0.000ns 0.000ns 1.513ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.828 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.828 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns sclrp 1 PIN PIN_M21 97 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 97; PIN Node = 'sclrp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclrp } "NODE_NAME" } } { "dds_top.vhd" "" { Text "D:/my_eda3/DDS/dds_top.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.880 ns) + CELL(0.223 ns) 2.828 ns DDS:DDSi\|SDelay:Delayi\|result\[9\] 2 REG LC_X31_Y26_N2 3 " "Info: 2: + IC(1.880 ns) + CELL(0.223 ns) = 2.828 ns; Loc. = LC_X31_Y26_N2; Fanout = 3; REG Node = 'DDS:DDSi\|SDelay:Delayi\|result\[9\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.103 ns" { sclrp DDS:DDSi|SDelay:Delayi|result[9] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.948 ns ( 33.52 % ) " "Info: Total cell delay = 0.948 ns ( 33.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.880 ns ( 66.48 % ) " "Info: Total interconnect delay = 1.880 ns ( 66.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.828 ns" { sclrp DDS:DDSi|SDelay:Delayi|result[9] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.828 ns" { sclrp sclrp~out0 DDS:DDSi|SDelay:Delayi|result[9] } { 0.000ns 0.000ns 1.880ns } { 0.000ns 0.725ns 0.223ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.883 ns" { clock DDS:DDSi|SDelay:Delayi|result[9] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.883 ns" { clock clock~out0 DDS:DDSi|SDelay:Delayi|result[9] } { 0.000ns 0.000ns 1.513ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.828 ns" { sclrp DDS:DDSi|SDelay:Delayi|result[9] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.828 ns" { sclrp sclrp~out0 DDS:DDSi|SDelay:Delayi|result[9] } { 0.000ns 0.000ns 1.880ns } { 0.000ns 0.725ns 0.223ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}