dds_top.tan.qmsg

在quartus开发环境下

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "dds_top.vhd" "" { Text "D:/my_eda3/DDS/dds_top.vhd" 34 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clock memory DDS:DDSi\|altsyncram:Mux0_rtl_0\|altsyncram_bju:auto_generated\|ram_block1a1~porta_address_reg9 register DDS:DDSi\|AltiMult:Producti\|resdtb\[12\] 8.518 ns " "Info: Slack time is 8.518 ns for clock \"clock\" between source memory \"DDS:DDSi\|altsyncram:Mux0_rtl_0\|altsyncram_bju:auto_generated\|ram_block1a1~porta_address_reg9\" and destination register \"DDS:DDSi\|AltiMult:Producti\|resdtb\[12\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "87.09 MHz 11.482 ns " "Info: Fmax is 87.09 MHz (period= 11.482 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.595 ns + Largest memory register " "Info: + Largest memory to register requirement is 19.595 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.025 ns + Largest " "Info: + Largest clock skew is 0.025 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.024 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.024 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dds_top.vhd" "" { Text "D:/my_eda3/DDS/dds_top.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.654 ns) + CELL(0.542 ns) 3.024 ns DDS:DDSi\|AltiMult:Producti\|resdtb\[12\] 2 REG LC_X45_Y14_N5 1 " "Info: 2: + IC(1.654 ns) + CELL(0.542 ns) = 3.024 ns; Loc. = LC_X45_Y14_N5; Fanout = 1; REG Node = 'DDS:DDSi\|AltiMult:Producti\|resdtb\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.196 ns" { clock DDS:DDSi|AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.30 % ) " "Info: Total cell delay = 1.370 ns ( 45.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.654 ns ( 54.70 % ) " "Info: Total interconnect delay = 1.654 ns ( 54.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.024 ns" { clock DDS:DDSi|AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.024 ns" { clock clock~out0 DDS:DDSi|AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.654ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.999 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dds_top.vhd" "" { Text "D:/my_eda3/DDS/dds_top.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.659 ns) + CELL(0.512 ns) 2.999 ns DDS:DDSi\|altsyncram:Mux0_rtl_0\|altsyncram_bju:auto_generated\|ram_block1a1~porta_address_reg9 2 MEM M4K_X37_Y18 2 " "Info: 2: + IC(1.659 ns) + CELL(0.512 ns) = 2.999 ns; Loc. = M4K_X37_Y18; Fanout = 2; MEM Node = 'DDS:DDSi\|altsyncram:Mux0_rtl_0\|altsyncram_bju:auto_generated\|ram_block1a1~porta_address_reg9'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.171 ns" { clock DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_bju.tdf" "" { Text "D:/my_eda3/DDS/db/altsyncram_bju.tdf" 61 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.340 ns ( 44.68 % ) " "Info: Total cell delay = 1.340 ns ( 44.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.659 ns ( 55.32 % ) " "Info: Total interconnect delay = 1.659 ns ( 55.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clock DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clock clock~out0 DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.512ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.024 ns" { clock DDS:DDSi|AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.024 ns" { clock clock~out0 DDS:DDSi|AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.654ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clock DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clock clock~out0 DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.512ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns - " "Info: - Micro clock to output delay of source is 0.420 ns" {  } { { "db/altsyncram_bju.tdf" "" { Text "D:/my_eda3/DDS/db/altsyncram_bju.tdf" 61 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.024 ns" { clock DDS:DDSi|AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.024 ns" { clock clock~out0 DDS:DDSi|AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.654ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clock DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clock clock~out0 DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.512ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.077 ns - Longest memory register " "Info: - Longest memory to register delay is 11.077 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DDS:DDSi\|altsyncram:Mux0_rtl_0\|altsyncram_bju:auto_generated\|ram_block1a1~porta_address_reg9 1 MEM M4K_X37_Y18 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X37_Y18; Fanout = 2; MEM Node = 'DDS:DDSi\|altsyncram:Mux0_rtl_0\|altsyncram_bju:auto_generated\|ram_block1a1~porta_address_reg9'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_bju.tdf" "" { Text "D:/my_eda3/DDS/db/altsyncram_bju.tdf" 61 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.069 ns) 3.069 ns DDS:DDSi\|altsyncram:Mux0_rtl_0\|altsyncram_bju:auto_generated\|q_a\[0\] 2 MEM M4K_X37_Y18 1 " "Info: 2: + IC(0.000 ns) + CELL(3.069 ns) = 3.069 ns; Loc. = M4K_X37_Y18; Fanout = 1; MEM Node = 'DDS:DDSi\|altsyncram:Mux0_rtl_0\|altsyncram_bju:auto_generated\|q_a\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.069 ns" { DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_bju.tdf" "" { Text "D:/my_eda3/DDS/db/altsyncram_bju.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.075 ns) 4.153 ns DDS:DDSi\|AltiMult:Producti\|dataaint~212 3 COMB LC_X39_Y17_N6 22 " "Info: 3: + IC(1.009 ns) + CELL(0.075 ns) = 4.153 ns; Loc. = LC_X39_Y17_N6; Fanout = 22; COMB Node = 'DDS:DDSi\|AltiMult:Producti\|dataaint~212'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.084 ns" { DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|q_a[0] DDS:DDSi|AltiMult:Producti|dataaint~212 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1622 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.273 ns) + CELL(3.451 ns) 8.877 ns DDS:DDSi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|mac_mult2~DATAOUT21 4 COMB DSPMULT_X42_Y15_N0 10 " "Info: 4: + IC(1.273 ns) + CELL(3.451 ns) = 8.877 ns; Loc. = DSPMULT_X42_Y15_N0; Fanout = 10; COMB Node = 'DDS:DDSi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|mac_mult2~DATAOUT21'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.724 ns" { DDS:DDSi|AltiMult:Producti|dataaint~212 DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 } "NODE_NAME" } } { "db/mult_6h01.tdf" "" { Text "D:/my_eda3/DDS/db/mult_6h01.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.878 ns) 9.755 ns DDS:DDSi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|result\[12\] 5 COMB DSPOUT_X43_Y9_N0 1 " "Info: 5: + IC(0.000 ns) + CELL(0.878 ns) = 9.755 ns; Loc. = DSPOUT_X43_Y9_N0; Fanout = 1; COMB Node = 'DDS:DDSi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|result\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.878 ns" { DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] } "NODE_NAME" } } { "db/mult_6h01.tdf" "" { Text "D:/my_eda3/DDS/db/mult_6h01.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.099 ns) + CELL(0.223 ns) 11.077 ns DDS:DDSi\|AltiMult:Producti\|resdtb\[12\] 6 REG LC_X45_Y14_N5 1 " "Info: 6: + IC(1.099 ns) + CELL(0.223 ns) = 11.077 ns; Loc. = LC_X45_Y14_N5; Fanout = 1; REG Node = 'DDS:DDSi\|AltiMult:Producti\|resdtb\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.322 ns" { DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] DDS:DDSi|AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.696 ns ( 69.48 % ) " "Info: Total cell delay = 7.696 ns ( 69.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.381 ns ( 30.52 % ) " "Info: Total interconnect delay = 3.381 ns ( 30.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.077 ns" { DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|q_a[0] DDS:DDSi|AltiMult:Producti|dataaint~212 DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] DDS:DDSi|AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.077 ns" { DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|q_a[0] DDS:DDSi|AltiMult:Producti|dataaint~212 DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] DDS:DDSi|AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.009ns 1.273ns 0.000ns 1.099ns } { 0.000ns 3.069ns 0.075ns 3.451ns 0.878ns 0.223ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.024 ns" { clock DDS:DDSi|AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.024 ns" { clock clock~out0 DDS:DDSi|AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.654ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clock DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clock clock~out0 DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.512ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.077 ns" { DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|q_a[0] DDS:DDSi|AltiMult:Producti|dataaint~212 DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] DDS:DDSi|AltiMult:Producti|resdtb[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.077 ns" { DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|q_a[0] DDS:DDSi|AltiMult:Producti|dataaint~212 DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[12] DDS:DDSi|AltiMult:Producti|resdtb[12] } { 0.000ns 0.000ns 1.009ns 1.273ns 0.000ns 1.099ns } { 0.000ns 3.069ns 0.075ns 3.451ns 0.878ns 0.223ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock register DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\] register DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\] 886 ps " "Info: Minimum slack time is 886 ps for clock \"clock\" between source register \"DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\]\" and destination register \"DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.830 ns + Shortest register register " "Info: + Shortest register to register delay is 0.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\] 1 REG LC_X32_Y22_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y22_N1; Fanout = 3; REG Node = 'DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.458 ns) 0.830 ns DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\] 2 REG LC_X32_Y22_N1 3 " "Info: 2: + IC(0.372 ns) + CELL(0.458 ns) = 0.830 ns; Loc. = LC_X32_Y22_N1; Fanout = 3; REG Node = 'DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.830 ns" { DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.458 ns ( 55.18 % ) " "Info: Total cell delay = 0.458 ns ( 55.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.372 ns ( 44.82 % ) " "Info: Total interconnect delay = 0.372 ns ( 44.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.830 ns" { DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.830 ns" { DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } { 0.000ns 0.372ns } { 0.000ns 0.458ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.056 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.056 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.918 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.918 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dds_top.vhd" "" { Text "D:/my_eda3/DDS/dds_top.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.548 ns) + CELL(0.542 ns) 2.918 ns DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\] 2 REG LC_X32_Y22_N1 3 " "Info: 2: + IC(1.548 ns) + CELL(0.542 ns) = 2.918 ns; Loc. = LC_X32_Y22_N1; Fanout = 3; REG Node = 'DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.090 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.95 % ) " "Info: Total cell delay = 1.370 ns ( 46.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.548 ns ( 53.05 % ) " "Info: Total interconnect delay = 1.548 ns ( 53.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.918 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.918 ns" { clock clock~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } { 0.000ns 0.000ns 1.548ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.918 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to source register is 2.918 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 127 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 127; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dds_top.vhd" "" { Text "D:/my_eda3/DDS/dds_top.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.548 ns) + CELL(0.542 ns) 2.918 ns DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\] 2 REG LC_X32_Y22_N1 3 " "Info: 2: + IC(1.548 ns) + CELL(0.542 ns) = 2.918 ns; Loc. = LC_X32_Y22_N1; Fanout = 3; REG Node = 'DDS:DDSi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.090 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.95 % ) " "Info: Total cell delay = 1.370 ns ( 46.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.548 ns ( 53.05 % ) " "Info: Total interconnect delay = 1.548 ns ( 53.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.918 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.918 ns" { clock clock~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } { 0.000ns 0.000ns 1.548ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.918 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.918 ns" { clock clock~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } { 0.000ns 0.000ns 1.548ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.918 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.918 ns" { clock clock~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } { 0.000ns 0.000ns 1.548ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns - " "Info: - Micro clock to output delay of source is 0.156 ns" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.918 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.918 ns" { clock clock~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } { 0.000ns 0.000ns 1.548ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.918 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.918 ns" { clock clock~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } { 0.000ns 0.000ns 1.548ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.830 ns" { DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.830 ns" { DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } { 0.000ns 0.372ns } { 0.000ns 0.458ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.918 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.918 ns" { clock clock~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } { 0.000ns 0.000ns 1.548ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.918 ns" { clock DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.918 ns" { clock clock~out0 DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10] } { 0.000ns 0.000ns 1.548ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}