dds.fit.qmsg

在quartus开发环境下

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "11.103 ns memory register " "Info: Estimated most critical path is memory to register delay of 11.103 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|ram_block1a1~porta_address_reg9 1 MEM M4K_X15_Y18 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X15_Y18; Fanout = 1; MEM Node = 'altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|ram_block1a1~porta_address_reg9'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_p5u.tdf" "" { Text "D:/my_eda3/DDS/db/altsyncram_p5u.tdf" 61 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.069 ns) 3.069 ns altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|q_a\[1\] 2 MEM M4K_X15_Y18 1 " "Info: 2: + IC(0.000 ns) + CELL(3.069 ns) = 3.069 ns; Loc. = M4K_X15_Y18; Fanout = 1; MEM Node = 'altsyncram:Mux0_rtl_0\|altsyncram_p5u:auto_generated\|q_a\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.069 ns" { altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|q_a[1] } "NODE_NAME" } } { "db/altsyncram_p5u.tdf" "" { Text "D:/my_eda3/DDS/db/altsyncram_p5u.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.032 ns) + CELL(0.280 ns) 4.381 ns AltiMult:Producti\|dataaint~211 3 COMB LAB_X12_Y16 22 " "Info: 3: + IC(1.032 ns) + CELL(0.280 ns) = 4.381 ns; Loc. = LAB_X12_Y16; Fanout = 22; COMB Node = 'AltiMult:Producti\|dataaint~211'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.312 ns" { altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|q_a[1] AltiMult:Producti|dataaint~211 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1622 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(3.451 ns) 8.748 ns AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|mac_mult2~DATAOUT21 4 COMB DSPMULT_X10_Y15_N0 10 " "Info: 4: + IC(0.916 ns) + CELL(3.451 ns) = 8.748 ns; Loc. = DSPMULT_X10_Y15_N0; Fanout = 10; COMB Node = 'AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|mac_mult2~DATAOUT21'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.367 ns" { AltiMult:Producti|dataaint~211 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 } "NODE_NAME" } } { "db/mult_6h01.tdf" "" { Text "D:/my_eda3/DDS/db/mult_6h01.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.878 ns) 9.626 ns AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|result\[11\] 5 COMB DSPOUT_X11_Y9_N0 1 " "Info: 5: + IC(0.000 ns) + CELL(0.878 ns) = 9.626 ns; Loc. = DSPOUT_X11_Y9_N0; Fanout = 1; COMB Node = 'AltiMult:Producti\|lpm_mult:Mult0\|mult_6h01:auto_generated\|result\[11\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.878 ns" { AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[11] } "NODE_NAME" } } { "db/mult_6h01.tdf" "" { Text "D:/my_eda3/DDS/db/mult_6h01.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.938 ns) + CELL(0.539 ns) 11.103 ns AltiMult:Producti\|resdtb\[11\] 6 REG LAB_X9_Y19 1 " "Info: 6: + IC(0.938 ns) + CELL(0.539 ns) = 11.103 ns; Loc. = LAB_X9_Y19; Fanout = 1; REG Node = 'AltiMult:Producti\|resdtb\[11\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[11] AltiMult:Producti|resdtb[11] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.217 ns ( 74.01 % ) " "Info: Total cell delay = 8.217 ns ( 74.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.886 ns ( 25.99 % ) " "Info: Total interconnect delay = 2.886 ns ( 25.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.103 ns" { altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|ram_block1a1~porta_address_reg9 altsyncram:Mux0_rtl_0|altsyncram_p5u:auto_generated|q_a[1] AltiMult:Producti|dataaint~211 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21 AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[11] AltiMult:Producti|resdtb[11] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X10_Y10 X20_Y20 " "Info: The peak interconnect region extends from location X10_Y10 to location X20_Y20" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}