prev_cmp_m.map.qmsg

来自「在quartus开发环境下」· QMSG 代码 · 共 20 行 · 第 1/4 页

{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\" DSP Builder - Quartus II development tool and MATLAB/Simulink Interface - Version 6.0\" m.vhd(54) " "Info (10544): VHDL Assertion Statement at m.vhd(54): assertion is false - report \" DSP Builder - Quartus II development tool and MATLAB/Simulink Interface - Version 6.0\" (NOTE)" {  } { { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 54 0 0 } }  } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SDelay SDelay:Delayi " "Info: Elaborating entity \"SDelay\" for hierarchy \"SDelay:Delayi\"" {  } { { "m.vhd" "Delayi" { Text "D:/my_eda3/m/m.vhd" 72 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sAltrPropagate SDelay:Delayi\|sAltrPropagate:u0 " "Info: Elaborating entity \"sAltrPropagate\" for hierarchy \"SDelay:Delayi\|sAltrPropagate:u0\"" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "u0" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1297 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SDelay SDelay:Delay1i " "Info: Elaborating entity \"SDelay\" for hierarchy \"SDelay:Delay1i\"" {  } { { "m.vhd" "Delay1i" { Text "D:/my_eda3/m/m.vhd" 85 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SDelay SDelay:Delay2i " "Info: Elaborating entity \"SDelay\" for hierarchy \"SDelay:Delay2i\"" {  } { { "m.vhd" "Delay2i" { Text "D:/my_eda3/m/m.vhd" 98 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}