prev_cmp_m.tan.qmsg

在quartus开发环境下

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clock register SDelay:Delay1i\|DelayLine\[1\]\[0\] register SDelay:Delayi\|result\[0\] 18.936 ns " "Info: Slack time is 18.936 ns for clock \"clock\" between source register \"SDelay:Delay1i\|DelayLine\[1\]\[0\]\" and destination register \"SDelay:Delayi\|result\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "420.17 MHz " "Info: Fmax is restricted to 420.17 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.786 ns + Largest register register " "Info: + Largest register to register requirement is 19.786 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.349 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.349 ns SDelay:Delayi\|result\[0\] 3 REG LCFF_X1_Y4_N25 1 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N25; Fanout = 1; REG Node = 'SDelay:Delayi\|result\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clock~clkctrl SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.96 % ) " "Info: Total cell delay = 1.526 ns ( 64.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.04 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delayi|result[0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.349 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.349 ns SDelay:Delay1i\|DelayLine\[1\]\[0\] 3 REG LCFF_X1_Y4_N11 2 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i\|DelayLine\[1\]\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.96 % ) " "Info: Total cell delay = 1.526 ns ( 64.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.04 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delayi|result[0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delayi|result[0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.850 ns - Longest register register " "Info: - Longest register to register delay is 0.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDelay:Delay1i\|DelayLine\[1\]\[0\] 1 REG LCFF_X1_Y4_N11 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i\|DelayLine\[1\]\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.491 ns) + CELL(0.275 ns) 0.766 ns SDelay:Delayi\|result~14 2 COMB LCCOMB_X1_Y4_N24 1 " "Info: 2: + IC(0.491 ns) + CELL(0.275 ns) = 0.766 ns; Loc. = LCCOMB_X1_Y4_N24; Fanout = 1; COMB Node = 'SDelay:Delayi\|result~14'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.766 ns" { SDelay:Delay1i|DelayLine[1][0] SDelay:Delayi|result~14 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1282 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.850 ns SDelay:Delayi\|result\[0\] 3 REG LCFF_X1_Y4_N25 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.850 ns; Loc. = LCFF_X1_Y4_N25; Fanout = 1; REG Node = 'SDelay:Delayi\|result\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { SDelay:Delayi|result~14 SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.359 ns ( 42.24 % ) " "Info: Total cell delay = 0.359 ns ( 42.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.491 ns ( 57.76 % ) " "Info: Total interconnect delay = 0.491 ns ( 57.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.850 ns" { SDelay:Delay1i|DelayLine[1][0] SDelay:Delayi|result~14 SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.850 ns" { SDelay:Delay1i|DelayLine[1][0] SDelay:Delayi|result~14 SDelay:Delayi|result[0] } { 0.000ns 0.491ns 0.000ns } { 0.000ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delayi|result[0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.850 ns" { SDelay:Delay1i|DelayLine[1][0] SDelay:Delayi|result~14 SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.850 ns" { SDelay:Delay1i|DelayLine[1][0] SDelay:Delayi|result~14 SDelay:Delayi|result[0] } { 0.000ns 0.491ns 0.000ns } { 0.000ns 0.275ns 0.084ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock register SDelay:Delay1i\|DelayLine\[0\]\[0\] register SDelay:Delay1i\|DelayLine\[1\]\[0\] 517 ps " "Info: Minimum slack time is 517 ps for clock \"clock\" between source register \"SDelay:Delay1i\|DelayLine\[0\]\[0\]\" and destination register \"SDelay:Delay1i\|DelayLine\[1\]\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.533 ns + Shortest register register " "Info: + Shortest register to register delay is 0.533 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDelay:Delay1i\|DelayLine\[0\]\[0\] 1 REG LCFF_X1_Y4_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 1; REG Node = 'SDelay:Delay1i\|DelayLine\[0\]\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDelay:Delay1i|DelayLine[0][0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.299 ns) + CELL(0.150 ns) 0.449 ns SDelay:Delay1i\|DelayLine~21 2 COMB LCCOMB_X1_Y4_N10 1 " "Info: 2: + IC(0.299 ns) + CELL(0.150 ns) = 0.449 ns; Loc. = LCCOMB_X1_Y4_N10; Fanout = 1; COMB Node = 'SDelay:Delay1i\|DelayLine~21'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.449 ns" { SDelay:Delay1i|DelayLine[0][0] SDelay:Delay1i|DelayLine~21 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1289 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.533 ns SDelay:Delay1i\|DelayLine\[1\]\[0\] 3 REG LCFF_X1_Y4_N11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.533 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i\|DelayLine\[1\]\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { SDelay:Delay1i|DelayLine~21 SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.234 ns ( 43.90 % ) " "Info: Total cell delay = 0.234 ns ( 43.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.299 ns ( 56.10 % ) " "Info: Total interconnect delay = 0.299 ns ( 56.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.533 ns" { SDelay:Delay1i|DelayLine[0][0] SDelay:Delay1i|DelayLine~21 SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.533 ns" { SDelay:Delay1i|DelayLine[0][0] SDelay:Delay1i|DelayLine~21 SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.299ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.016 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.016 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.349 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.349 ns SDelay:Delay1i\|DelayLine\[1\]\[0\] 3 REG LCFF_X1_Y4_N11 2 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i\|DelayLine\[1\]\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.96 % ) " "Info: Total cell delay = 1.526 ns ( 64.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.04 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.349 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to source register is 2.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.349 ns SDelay:Delay1i\|DelayLine\[0\]\[0\] 3 REG LCFF_X1_Y4_N1 1 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 1; REG Node = 'SDelay:Delay1i\|DelayLine\[0\]\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clock~clkctrl SDelay:Delay1i|DelayLine[0][0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.96 % ) " "Info: Total cell delay = 1.526 ns ( 64.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.04 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[0][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[0][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[0][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[0][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[0][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[0][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.533 ns" { SDelay:Delay1i|DelayLine[0][0] SDelay:Delay1i|DelayLine~21 SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.533 ns" { SDelay:Delay1i|DelayLine[0][0] SDelay:Delay1i|DelayLine~21 SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.299ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[0][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[0][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}