m.fit.rpt

在quartus开发环境下

+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
; |m                         ; 10 (0)      ; 10 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 3    ; 0            ; 0 (0)        ; 0 (0)             ; 10 (0)           ; |m                  ; work         ;
;    |SDelay:Delay1i|        ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; |m|SDelay:Delay1i   ; work         ;
;    |SDelay:Delay2i|        ; 7 (7)       ; 7 (7)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; |m|SDelay:Delay2i   ; work         ;
;    |SDelay:Delayi|         ; 1 (1)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |m|SDelay:Delayi    ; work         ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------+
; Delay Chain Summary                                                             ;
+--------+----------+---------------+---------------+-----------------------+-----+
; Name   ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+--------+----------+---------------+---------------+-----------------------+-----+
; Output ; Output   ; --            ; --            ; --                    ; --  ;
; sclrp  ; Input    ; 6             ; 6             ; --                    ; --  ;
; clock  ; Input    ; 0             ; 0             ; --                    ; --  ;
+--------+----------+---------------+---------------+-----------------------+-----+


+-------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout                                    ;
+-------------------------------------+-------------------+---------+
; Source Pin / Fanout                 ; Pad To Core Index ; Setting ;
+-------------------------------------+-------------------+---------+
; sclrp                               ;                   ;         ;
;      - SDelay:Delay2i|DelayLine~100 ; 0                 ; 6       ;
;      - SDelay:Delay2i|DelayLine~101 ; 0                 ; 6       ;
;      - SDelay:Delay2i|DelayLine~102 ; 0                 ; 6       ;
;      - SDelay:Delay2i|DelayLine~103 ; 0                 ; 6       ;
;      - SDelay:Delay2i|DelayLine~104 ; 0                 ; 6       ;
;      - SDelay:Delay2i|DelayLine~105 ; 0                 ; 6       ;
;      - SDelay:Delay2i|DelayLine~106 ; 0                 ; 6       ;
;      - SDelay:Delay1i|DelayLine~21  ; 0                 ; 6       ;
;      - SDelay:Delay1i|DelayLine~22  ; 0                 ; 6       ;
;      - SDelay:Delayi|result~14      ; 0                 ; 6       ;
; clock                               ;                   ;         ;
+-------------------------------------+-------------------+---------+


+-------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                   ;
+-------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
; Name  ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
; clock ; PIN_17   ; 10      ; Clock ; yes    ; Global Clock         ; GCLK2            ; --                        ;
+-------+----------+---------+-------+--------+----------------------+------------------+---------------------------+


+--------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                      ;
+-------+----------+---------+----------------------+------------------+---------------------------+
; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-------+----------+---------+----------------------+------------------+---------------------------+
; clock ; PIN_17   ; 10      ; Global Clock         ; GCLK2            ; --                        ;
+-------+----------+---------+----------------------+------------------+---------------------------+


+------------------------------------------+
; Non-Global High Fan-Out Signals          ;
+--------------------------------+---------+
; Name                           ; Fan-Out ;
+--------------------------------+---------+
; sclrp                          ; 10      ;
; SDelay:Delay1i|DelayLine[1][0] ; 2       ;
; SDelay:Delay2i|DelayLine[6][0] ; 2       ;
; SDelay:Delayi|result~14        ; 1       ;
; SDelay:Delay1i|DelayLine~22    ; 1       ;
; SDelay:Delayi|result[0]        ; 1       ;
; SDelay:Delay1i|DelayLine~21    ; 1       ;
; SDelay:Delay1i|DelayLine[0][0] ; 1       ;
; SDelay:Delay2i|DelayLine~106   ; 1       ;
; SDelay:Delay2i|DelayLine~105   ; 1       ;
; SDelay:Delay2i|DelayLine[0][0] ; 1       ;
; SDelay:Delay2i|DelayLine~104   ; 1       ;
; SDelay:Delay2i|DelayLine[1][0] ; 1       ;
; SDelay:Delay2i|DelayLine~103   ; 1       ;
; SDelay:Delay2i|DelayLine[2][0] ; 1       ;
; SDelay:Delay2i|DelayLine~102   ; 1       ;
; SDelay:Delay2i|DelayLine[3][0] ; 1       ;
; SDelay:Delay2i|DelayLine~101   ; 1       ;
; SDelay:Delay2i|DelayLine[4][0] ; 1       ;
; SDelay:Delay2i|DelayLine~100   ; 1       ;
; SDelay:Delay2i|DelayLine[5][0] ; 1       ;
+--------------------------------+---------+


+---------------------------------------------------+
; Interconnect Usage Summary                        ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage                ;
+----------------------------+----------------------+
; Block interconnects        ; 4 / 15,666 ( < 1 % ) ;
; C16 interconnects          ; 0 / 812 ( 0 % )      ;
; C4 interconnects           ; 1 / 11,424 ( < 1 % ) ;
; Direct links               ; 3 / 15,666 ( < 1 % ) ;
; Global clocks              ; 1 / 8 ( 13 % )       ;
; Local interconnects        ; 9 / 4,608 ( < 1 % )  ;
; R24 interconnects          ; 0 / 652 ( 0 % )      ;
; R4 interconnects           ; 0 / 13,328 ( 0 % )   ;
+----------------------------+----------------------+


+---------------------------------------------------------------------------+
; LAB Logic Elements                                                        ;
+---------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 10.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 1                           ;
; 11                                          ; 0                           ;
; 12                                          ; 0                           ;
; 13                                          ; 0                           ;
; 14                                          ; 0                           ;
; 15                                          ; 0                           ;
; 16                                          ; 0                           ;
+---------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+------------------------------------+-----------------------------+