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SourceType "SignalCompiler"
family "Cyclone II"
opt "Balanced"
synthtool "Others"
vstim on
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workdir "D:\\my_eda3\\m"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation off
JTAGCable "USB-Blaster [USB-0]"
dspb_ver "6.1"
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