fsk.tan.qmsg

在quartus开发环境下

{ "Info" "ITDB_TSU_RESULT" "dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\] Pword\[0\] clock 3.452 ns register " "Info: tsu for register \"dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\]\" (data pin = \"Pword\[0\]\", clock pin = \"clock\") is 3.452 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.478 ns + Longest pin register " "Info: + Longest pin to register delay is 6.478 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns Pword\[0\] 1 PIN PIN_P16 3 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_P16; Fanout = 3; PIN Node = 'Pword\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Pword[0] } "NODE_NAME" } } { "FSK.vhd" "" { Text "D:/my_eda3/ASK_FSK/FSK.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.373 ns) + CELL(0.341 ns) 5.801 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[2\]~24COUT1 2 COMB LC_X14_Y12_N0 2 " "Info: 2: + IC(4.373 ns) + CELL(0.341 ns) = 5.801 ns; Loc. = LC_X14_Y12_N0; Fanout = 2; COMB Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[2\]~24COUT1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.714 ns" { Pword[0] dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~24COUT1 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 5.861 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~25COUT1 3 COMB LC_X14_Y12_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 5.861 ns; Loc. = LC_X14_Y12_N1; Fanout = 2; COMB Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~25COUT1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~24COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~25COUT1 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 5.921 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\]~26COUT1 4 COMB LC_X14_Y12_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 5.921 ns; Loc. = LC_X14_Y12_N2; Fanout = 2; COMB Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\]~26COUT1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~25COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~26COUT1 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 5.981 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[5\]~27COUT1 5 COMB LC_X14_Y12_N3 1 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 5.981 ns; Loc. = LC_X14_Y12_N3; Fanout = 1; COMB Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[5\]~27COUT1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~26COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~27COUT1 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.497 ns) 6.478 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\] 6 REG LC_X14_Y12_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.497 ns) = 6.478 ns; Loc. = LC_X14_Y12_N4; Fanout = 3; REG Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.497 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~27COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.105 ns ( 32.49 % ) " "Info: Total cell delay = 2.105 ns ( 32.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.373 ns ( 67.51 % ) " "Info: Total interconnect delay = 4.373 ns ( 67.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.478 ns" { Pword[0] dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~24COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~25COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~26COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~27COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.478 ns" { Pword[0] Pword[0]~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~24COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~25COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~26COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~27COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] } { 0.000ns 0.000ns 4.373ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.087ns 0.341ns 0.060ns 0.060ns 0.060ns 0.497ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.036 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 3.036 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 91 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 91; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "FSK.vhd" "" { Text "D:/my_eda3/ASK_FSK/FSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.666 ns) + CELL(0.542 ns) 3.036 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\] 2 REG LC_X14_Y12_N4 3 " "Info: 2: + IC(1.666 ns) + CELL(0.542 ns) = 3.036 ns; Loc. = LC_X14_Y12_N4; Fanout = 3; REG Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractor1i\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.208 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.13 % ) " "Info: Total cell delay = 1.370 ns ( 45.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.666 ns ( 54.87 % ) " "Info: Total interconnect delay = 1.666 ns ( 54.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.036 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.036 ns" { clock clock~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] } { 0.000ns 0.000ns 1.666ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.478 ns" { Pword[0] dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~24COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~25COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~26COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~27COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.478 ns" { Pword[0] Pword[0]~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~24COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~25COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~26COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~27COUT1 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] } { 0.000ns 0.000ns 4.373ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.087ns 0.341ns 0.060ns 0.060ns 0.060ns 0.497ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.036 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.036 ns" { clock clock~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] } { 0.000ns 0.000ns 1.666ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock data_out\[3\] dds:ddsi\|AltiMult:Producti\|resdtb\[13\] 7.409 ns register " "Info: tco from clock \"clock\" to destination pin \"data_out\[3\]\" through register \"dds:ddsi\|AltiMult:Producti\|resdtb\[13\]\" is 7.409 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.061 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 91 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 91; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "FSK.vhd" "" { Text "D:/my_eda3/ASK_FSK/FSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.691 ns) + CELL(0.542 ns) 3.061 ns dds:ddsi\|AltiMult:Producti\|resdtb\[13\] 2 REG LC_X9_Y15_N2 1 " "Info: 2: + IC(1.691 ns) + CELL(0.542 ns) = 3.061 ns; Loc. = LC_X9_Y15_N2; Fanout = 1; REG Node = 'dds:ddsi\|AltiMult:Producti\|resdtb\[13\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.233 ns" { clock dds:ddsi|AltiMult:Producti|resdtb[13] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.76 % ) " "Info: Total cell delay = 1.370 ns ( 44.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.691 ns ( 55.24 % ) " "Info: Total interconnect delay = 1.691 ns ( 55.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.061 ns" { clock dds:ddsi|AltiMult:Producti|resdtb[13] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.061 ns" { clock clock~out0 dds:ddsi|AltiMult:Producti|resdtb[13] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.192 ns + Longest register pin " "Info: + Longest register to pin delay is 4.192 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds:ddsi\|AltiMult:Producti\|resdtb\[13\] 1 REG LC_X9_Y15_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y15_N2; Fanout = 1; REG Node = 'dds:ddsi\|AltiMult:Producti\|resdtb\[13\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds:ddsi|AltiMult:Producti|resdtb[13] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.788 ns) + CELL(2.404 ns) 4.192 ns data_out\[3\] 2 PIN PIN_G16 0 " "Info: 2: + IC(1.788 ns) + CELL(2.404 ns) = 4.192 ns; Loc. = PIN_G16; Fanout = 0; PIN Node = 'data_out\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.192 ns" { dds:ddsi|AltiMult:Producti|resdtb[13] data_out[3] } "NODE_NAME" } } { "FSK.vhd" "" { Text "D:/my_eda3/ASK_FSK/FSK.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 57.35 % ) " "Info: Total cell delay = 2.404 ns ( 57.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.788 ns ( 42.65 % ) " "Info: Total interconnect delay = 1.788 ns ( 42.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.192 ns" { dds:ddsi|AltiMult:Producti|resdtb[13] data_out[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.192 ns" { dds:ddsi|AltiMult:Producti|resdtb[13] data_out[3] } { 0.000ns 1.788ns } { 0.000ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.061 ns" { clock dds:ddsi|AltiMult:Producti|resdtb[13] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.061 ns" { clock clock~out0 dds:ddsi|AltiMult:Producti|resdtb[13] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.192 ns" { dds:ddsi|AltiMult:Producti|resdtb[13] data_out[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.192 ns" { dds:ddsi|AltiMult:Producti|resdtb[13] data_out[3] } { 0.000ns 1.788ns } { 0.000ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "dds:ddsi\|AltiMult:Producti\|databint\[1\] sclrp clock 0.112 ns register " "Info: th for register \"dds:ddsi\|AltiMult:Producti\|databint\[1\]\" (data pin = \"sclrp\", clock pin = \"clock\") is 0.112 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.046 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 3.046 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 91 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 91; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "FSK.vhd" "" { Text "D:/my_eda3/ASK_FSK/FSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.542 ns) 3.046 ns dds:ddsi\|AltiMult:Producti\|databint\[1\] 2 REG LC_X8_Y13_N2 20 " "Info: 2: + IC(1.676 ns) + CELL(0.542 ns) = 3.046 ns; Loc. = LC_X8_Y13_N2; Fanout = 20; REG Node = 'dds:ddsi\|AltiMult:Producti\|databint\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.218 ns" { clock dds:ddsi|AltiMult:Producti|databint[1] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1665 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.98 % ) " "Info: Total cell delay = 1.370 ns ( 44.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.676 ns ( 55.02 % ) " "Info: Total interconnect delay = 1.676 ns ( 55.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.046 ns" { clock dds:ddsi|AltiMult:Producti|databint[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 dds:ddsi|AltiMult:Producti|databint[1] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1665 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.034 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns sclrp 1 PIN PIN_M21 61 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 61; PIN Node = 'sclrp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclrp } "NODE_NAME" } } { "FSK.vhd" "" { Text "D:/my_eda3/ASK_FSK/FSK.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.086 ns) + CELL(0.223 ns) 3.034 ns dds:ddsi\|AltiMult:Producti\|databint\[1\] 2 REG LC_X8_Y13_N2 20 " "Info: 2: + IC(2.086 ns) + CELL(0.223 ns) = 3.034 ns; Loc. = LC_X8_Y13_N2; Fanout = 20; REG Node = 'dds:ddsi\|AltiMult:Producti\|databint\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.309 ns" { sclrp dds:ddsi|AltiMult:Producti|databint[1] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1665 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.948 ns ( 31.25 % ) " "Info: Total cell delay = 0.948 ns ( 31.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.086 ns ( 68.75 % ) " "Info: Total interconnect delay = 2.086 ns ( 68.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.034 ns" { sclrp dds:ddsi|AltiMult:Producti|databint[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.034 ns" { sclrp sclrp~out0 dds:ddsi|AltiMult:Producti|databint[1] } { 0.000ns 0.000ns 2.086ns } { 0.000ns 0.725ns 0.223ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.046 ns" { clock dds:ddsi|AltiMult:Producti|databint[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 dds:ddsi|AltiMult:Producti|databint[1] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.034 ns" { sclrp dds:ddsi|AltiMult:Producti|databint[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.034 ns" { sclrp sclrp~out0 dds:ddsi|AltiMult:Producti|databint[1] } { 0.000ns 0.000ns 2.086ns } { 0.000ns 0.725ns 0.223ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}