fsk.tan.qmsg

在quartus开发环境下

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "FSK.vhd" "" { Text "D:/my_eda3/ASK_FSK/FSK.vhd" 34 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clock memory dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|ram_block1a9~porta_address_reg9 register dds:ddsi\|AltiMult:Producti\|resdtb\[14\] 8.256 ns " "Info: Slack time is 8.256 ns for clock \"clock\" between source memory \"dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|ram_block1a9~porta_address_reg9\" and destination register \"dds:ddsi\|AltiMult:Producti\|resdtb\[14\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "85.15 MHz 11.744 ns " "Info: Fmax is 85.15 MHz (period= 11.744 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.607 ns + Largest memory register " "Info: + Largest memory to register requirement is 19.607 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.037 ns + Largest " "Info: + Largest clock skew is 0.037 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.016 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.016 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 91 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 91; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "FSK.vhd" "" { Text "D:/my_eda3/ASK_FSK/FSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.646 ns) + CELL(0.542 ns) 3.016 ns dds:ddsi\|AltiMult:Producti\|resdtb\[14\] 2 REG LC_X12_Y10_N2 1 " "Info: 2: + IC(1.646 ns) + CELL(0.542 ns) = 3.016 ns; Loc. = LC_X12_Y10_N2; Fanout = 1; REG Node = 'dds:ddsi\|AltiMult:Producti\|resdtb\[14\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.188 ns" { clock dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.42 % ) " "Info: Total cell delay = 1.370 ns ( 45.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.646 ns ( 54.58 % ) " "Info: Total interconnect delay = 1.646 ns ( 54.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.016 ns" { clock dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.016 ns" { clock clock~out0 dds:ddsi|AltiMult:Producti|resdtb[14] } { 0.000ns 0.000ns 1.646ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.979 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 2.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 91 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 91; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "FSK.vhd" "" { Text "D:/my_eda3/ASK_FSK/FSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.512 ns) 2.979 ns dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|ram_block1a9~porta_address_reg9 2 MEM M4K_X15_Y13 4 " "Info: 2: + IC(1.639 ns) + CELL(0.512 ns) = 2.979 ns; Loc. = M4K_X15_Y13; Fanout = 4; MEM Node = 'dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|ram_block1a9~porta_address_reg9'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.151 ns" { clock dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_26u.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_26u.tdf" 205 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.340 ns ( 44.98 % ) " "Info: Total cell delay = 1.340 ns ( 44.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 55.02 % ) " "Info: Total interconnect delay = 1.639 ns ( 55.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.979 ns" { clock dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.979 ns" { clock clock~out0 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.512ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.016 ns" { clock dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.016 ns" { clock clock~out0 dds:ddsi|AltiMult:Producti|resdtb[14] } { 0.000ns 0.000ns 1.646ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.979 ns" { clock dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.979 ns" { clock clock~out0 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.512ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns - " "Info: - Micro clock to output delay of source is 0.420 ns" {  } { { "db/altsyncram_26u.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_26u.tdf" 205 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.016 ns" { clock dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.016 ns" { clock clock~out0 dds:ddsi|AltiMult:Producti|resdtb[14] } { 0.000ns 0.000ns 1.646ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.979 ns" { clock dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.979 ns" { clock clock~out0 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.512ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.351 ns - Longest memory register " "Info: - Longest memory to register delay is 11.351 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|ram_block1a9~porta_address_reg9 1 MEM M4K_X15_Y13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X15_Y13; Fanout = 4; MEM Node = 'dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|ram_block1a9~porta_address_reg9'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_26u.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_26u.tdf" 205 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.069 ns) 3.069 ns dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|q_a\[8\] 2 MEM M4K_X15_Y13 1 " "Info: 2: + IC(0.000 ns) + CELL(3.069 ns) = 3.069 ns; Loc. = M4K_X15_Y13; Fanout = 1; MEM Node = 'dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|q_a\[8\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.069 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|q_a[8] } "NODE_NAME" } } { "db/altsyncram_26u.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_26u.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.298 ns) + CELL(0.075 ns) 4.442 ns dds:ddsi\|AltiMult:Producti\|dataaint~202 3 COMB LC_X13_Y15_N2 20 " "Info: 3: + IC(1.298 ns) + CELL(0.075 ns) = 4.442 ns; Loc. = LC_X13_Y15_N2; Fanout = 20; COMB Node = 'dds:ddsi\|AltiMult:Producti\|dataaint~202'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.373 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|q_a[8] dds:ddsi|AltiMult:Producti|dataaint~202 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1622 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.264 ns) + CELL(3.451 ns) 9.157 ns dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_2h01:auto_generated\|mac_mult2~DATAOUT19 4 COMB DSPMULT_X10_Y15_N0 10 " "Info: 4: + IC(1.264 ns) + CELL(3.451 ns) = 9.157 ns; Loc. = DSPMULT_X10_Y15_N0; Fanout = 10; COMB Node = 'dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_2h01:auto_generated\|mac_mult2~DATAOUT19'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.715 ns" { dds:ddsi|AltiMult:Producti|dataaint~202 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|mac_mult2~DATAOUT19 } "NODE_NAME" } } { "db/mult_2h01.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/mult_2h01.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.878 ns) 10.035 ns dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_2h01:auto_generated\|result\[14\] 5 COMB DSPOUT_X11_Y9_N0 1 " "Info: 5: + IC(0.000 ns) + CELL(0.878 ns) = 10.035 ns; Loc. = DSPOUT_X11_Y9_N0; Fanout = 1; COMB Node = 'dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_2h01:auto_generated\|result\[14\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.878 ns" { dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|mac_mult2~DATAOUT19 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|result[14] } "NODE_NAME" } } { "db/mult_2h01.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/mult_2h01.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.997 ns) + CELL(0.319 ns) 11.351 ns dds:ddsi\|AltiMult:Producti\|resdtb\[14\] 6 REG LC_X12_Y10_N2 1 " "Info: 6: + IC(0.997 ns) + CELL(0.319 ns) = 11.351 ns; Loc. = LC_X12_Y10_N2; Fanout = 1; REG Node = 'dds:ddsi\|AltiMult:Producti\|resdtb\[14\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.316 ns" { dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|result[14] dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.792 ns ( 68.65 % ) " "Info: Total cell delay = 7.792 ns ( 68.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.559 ns ( 31.35 % ) " "Info: Total interconnect delay = 3.559 ns ( 31.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.351 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|q_a[8] dds:ddsi|AltiMult:Producti|dataaint~202 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|mac_mult2~DATAOUT19 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|result[14] dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.351 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|q_a[8] dds:ddsi|AltiMult:Producti|dataaint~202 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|mac_mult2~DATAOUT19 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|result[14] dds:ddsi|AltiMult:Producti|resdtb[14] } { 0.000ns 0.000ns 1.298ns 1.264ns 0.000ns 0.997ns } { 0.000ns 3.069ns 0.075ns 3.451ns 0.878ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.016 ns" { clock dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.016 ns" { clock clock~out0 dds:ddsi|AltiMult:Producti|resdtb[14] } { 0.000ns 0.000ns 1.646ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.979 ns" { clock dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.979 ns" { clock clock~out0 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.512ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.351 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|q_a[8] dds:ddsi|AltiMult:Producti|dataaint~202 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|mac_mult2~DATAOUT19 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|result[14] dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.351 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a9~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|q_a[8] dds:ddsi|AltiMult:Producti|dataaint~202 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|mac_mult2~DATAOUT19 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|result[14] dds:ddsi|AltiMult:Producti|resdtb[14] } { 0.000ns 0.000ns 1.298ns 1.264ns 0.000ns 0.997ns } { 0.000ns 3.069ns 0.075ns 3.451ns 0.878ns 0.319ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock register dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\] register dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\] 885 ps " "Info: Minimum slack time is 885 ps for clock \"clock\" between source register \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\]\" and destination register \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.829 ns + Shortest register register " "Info: + Shortest register to register delay is 0.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\] 1 REG LC_X13_Y13_N0 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y13_N0; Fanout = 3; REG Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.458 ns) 0.829 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\] 2 REG LC_X13_Y13_N0 3 " "Info: 2: + IC(0.371 ns) + CELL(0.458 ns) = 0.829 ns; Loc. = LC_X13_Y13_N0; Fanout = 3; REG Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.829 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.458 ns ( 55.25 % ) " "Info: Total cell delay = 0.458 ns ( 55.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.371 ns ( 44.75 % ) " "Info: Total interconnect delay = 0.371 ns ( 44.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.829 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.829 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.371ns } { 0.000ns 0.458ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.056 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.056 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.046 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 3.046 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 91 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 91; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "FSK.vhd" "" { Text "D:/my_eda3/ASK_FSK/FSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.542 ns) 3.046 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\] 2 REG LC_X13_Y13_N0 3 " "Info: 2: + IC(1.676 ns) + CELL(0.542 ns) = 3.046 ns; Loc. = LC_X13_Y13_N0; Fanout = 3; REG Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.218 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.98 % ) " "Info: Total cell delay = 1.370 ns ( 44.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.676 ns ( 55.02 % ) " "Info: Total interconnect delay = 1.676 ns ( 55.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.046 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.046 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to source register is 3.046 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 91 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 91; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "FSK.vhd" "" { Text "D:/my_eda3/ASK_FSK/FSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.542 ns) 3.046 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\] 2 REG LC_X13_Y13_N0 3 " "Info: 2: + IC(1.676 ns) + CELL(0.542 ns) = 3.046 ns; Loc. = LC_X13_Y13_N0; Fanout = 3; REG Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|addcore:adder0\[0\]\|a_csnbuffer:result_node\|sout_node\[12\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.218 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.98 % ) " "Info: Total cell delay = 1.370 ns ( 44.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.676 ns ( 55.02 % ) " "Info: Total interconnect delay = 1.676 ns ( 55.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.046 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.046 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.046 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns - " "Info: - Micro clock to output delay of source is 0.156 ns" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.046 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.046 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.829 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.829 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.371ns } { 0.000ns 0.458ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.046 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.046 ns" { clock dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder0[0]|a_csnbuffer:result_node|sout_node[12] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}