fsk.fit.qmsg

在quartus开发环境下

{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "29 unused 3.30 19 10 0 " "Info: Number of I/O pins in group: 29 (unused VREF, 3.30 VCCIO, 19 input, 10 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 2 27 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  27 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 30 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 51 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 51 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 0 29 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 0 29 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 52 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 51 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "11.614 ns memory register " "Info: Estimated most critical path is memory to register delay of 11.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|ram_block1a1~porta_address_reg9 1 MEM M4K_X15_Y12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X15_Y12; Fanout = 1; MEM Node = 'dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|ram_block1a1~porta_address_reg9'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_26u.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_26u.tdf" 61 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.069 ns) 3.069 ns dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|q_a\[1\] 2 MEM M4K_X15_Y12 1 " "Info: 2: + IC(0.000 ns) + CELL(3.069 ns) = 3.069 ns; Loc. = M4K_X15_Y12; Fanout = 1; MEM Node = 'dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_26u:auto_generated\|q_a\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.069 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a1~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|q_a[1] } "NODE_NAME" } } { "db/altsyncram_26u.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_26u.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.280 ns) 4.388 ns dds:ddsi\|AltiMult:Producti\|dataaint~209 3 COMB LAB_X13_Y15 20 " "Info: 3: + IC(1.039 ns) + CELL(0.280 ns) = 4.388 ns; Loc. = LAB_X13_Y15; Fanout = 20; COMB Node = 'dds:ddsi\|AltiMult:Producti\|dataaint~209'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.319 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|q_a[1] dds:ddsi|AltiMult:Producti|dataaint~209 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1622 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.328 ns) + CELL(3.451 ns) 9.167 ns dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_2h01:auto_generated\|mac_mult2~DATAOUT19 4 COMB DSPMULT_X10_Y15_N0 10 " "Info: 4: + IC(1.328 ns) + CELL(3.451 ns) = 9.167 ns; Loc. = DSPMULT_X10_Y15_N0; Fanout = 10; COMB Node = 'dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_2h01:auto_generated\|mac_mult2~DATAOUT19'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.779 ns" { dds:ddsi|AltiMult:Producti|dataaint~209 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|mac_mult2~DATAOUT19 } "NODE_NAME" } } { "db/mult_2h01.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/mult_2h01.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.878 ns) 10.045 ns dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_2h01:auto_generated\|result\[11\] 5 COMB DSPOUT_X11_Y9_N0 1 " "Info: 5: + IC(0.000 ns) + CELL(0.878 ns) = 10.045 ns; Loc. = DSPOUT_X11_Y9_N0; Fanout = 1; COMB Node = 'dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_2h01:auto_generated\|result\[11\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.878 ns" { dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|mac_mult2~DATAOUT19 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|result[11] } "NODE_NAME" } } { "db/mult_2h01.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/mult_2h01.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.539 ns) 11.614 ns dds:ddsi\|AltiMult:Producti\|resdtb\[11\] 6 REG LAB_X9_Y10 1 " "Info: 6: + IC(1.030 ns) + CELL(0.539 ns) = 11.614 ns; Loc. = LAB_X9_Y10; Fanout = 1; REG Node = 'dds:ddsi\|AltiMult:Producti\|resdtb\[11\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.569 ns" { dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|result[11] dds:ddsi|AltiMult:Producti|resdtb[11] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.217 ns ( 70.75 % ) " "Info: Total cell delay = 8.217 ns ( 70.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.397 ns ( 29.25 % ) " "Info: Total interconnect delay = 3.397 ns ( 29.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.614 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|ram_block1a1~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated|q_a[1] dds:ddsi|AltiMult:Producti|dataaint~209 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|mac_mult2~DATAOUT19 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_2h01:auto_generated|result[11] dds:ddsi|AltiMult:Producti|resdtb[11] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}