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📄 mux_g4e.tdf

📁 在quartus开发环境下
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--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone II" IGNORE_CASCADE_BUFFERS="OFF" LPM_PIPELINE=0 LPM_SIZE=2 LPM_WIDTH=10 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 7.0 cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ  VERSION_END


--  Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 10 
SUBDESIGN mux_g4e
( 
	data[19..0]	:	input;
	result[9..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[9..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data102w[1..0]	: WIRE;
	w_data114w[1..0]	: WIRE;
	w_data18w[1..0]	: WIRE;
	w_data30w[1..0]	: WIRE;
	w_data42w[1..0]	: WIRE;
	w_data4w[1..0]	: WIRE;
	w_data54w[1..0]	: WIRE;
	w_data66w[1..0]	: WIRE;
	w_data78w[1..0]	: WIRE;
	w_data90w[1..0]	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( ((sel_node[] & w_data114w[1..1]) # ((! sel_node[]) & w_data114w[0..0])), ((sel_node[] & w_data102w[1..1]) # ((! sel_node[]) & w_data102w[0..0])), ((sel_node[] & w_data90w[1..1]) # ((! sel_node[]) & w_data90w[0..0])), ((sel_node[] & w_data78w[1..1]) # ((! sel_node[]) & w_data78w[0..0])), ((sel_node[] & w_data66w[1..1]) # ((! sel_node[]) & w_data66w[0..0])), ((sel_node[] & w_data54w[1..1]) # ((! sel_node[]) & w_data54w[0..0])), ((sel_node[] & w_data42w[1..1]) # ((! sel_node[]) & w_data42w[0..0])), ((sel_node[] & w_data30w[1..1]) # ((! sel_node[]) & w_data30w[0..0])), ((sel_node[] & w_data18w[1..1]) # ((! sel_node[]) & w_data18w[0..0])), ((sel_node[] & w_data4w[1..1]) # ((! sel_node[]) & w_data4w[0..0])));
	sel_node[] = ( sel[0..0]);
	w_data102w[] = ( data[18..18], data[8..8]);
	w_data114w[] = ( data[19..19], data[9..9]);
	w_data18w[] = ( data[11..11], data[1..1]);
	w_data30w[] = ( data[12..12], data[2..2]);
	w_data42w[] = ( data[13..13], data[3..3]);
	w_data4w[] = ( data[10..10], data[0..0]);
	w_data54w[] = ( data[14..14], data[4..4]);
	w_data66w[] = ( data[15..15], data[5..5]);
	w_data78w[] = ( data[16..16], data[6..6]);
	w_data90w[] = ( data[17..17], data[7..7]);
END;
--VALID FILE

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