📄 add_sub_bph.tdf
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--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="SIGNED" LPM_WIDTH=33 aclr clken clock dataa datab result
--VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ VERSION_END
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 33
SUBDESIGN add_sub_bph
(
aclr : input;
clken : input;
clock : input;
dataa[32..0] : input;
datab[32..0] : input;
result[32..0] : output;
)
VARIABLE
pipeline_dffe[32..0] : DFFE;
result_int[32..0] : WIRE;
BEGIN
result_int[] = dataa[] + datab[];
pipeline_dffe[].clk = clock;
pipeline_dffe[].clrn = !aclr;
pipeline_dffe[].ena = clken;
result[] = pipeline_dffe[32..0].q;
pipeline_dffe[32..0].d = result_int[];
END;
--VALID FILE
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