ask.fit.qmsg

在quartus开发环境下

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.798 ns memory register " "Info: Estimated most critical path is memory to register delay of 8.798 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|ram_block1a6~porta_address_reg9 1 MEM M4K_X23_Y12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X23_Y12; Fanout = 1; MEM Node = 'dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|ram_block1a6~porta_address_reg9'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_icu.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_icu.tdf" 163 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.993 ns) 2.993 ns dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|q_a\[6\] 2 MEM M4K_X23_Y12 1 " "Info: 2: + IC(0.000 ns) + CELL(2.993 ns) = 2.993 ns; Loc. = M4K_X23_Y12; Fanout = 1; MEM Node = 'dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|q_a\[6\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.993 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|q_a[6] } "NODE_NAME" } } { "db/altsyncram_icu.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_icu.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(0.420 ns) 4.557 ns dds:ddsi\|AltiMult:Producti\|dataaint~204 3 COMB LAB_X15_Y8 13 " "Info: 3: + IC(1.144 ns) + CELL(0.420 ns) = 4.557 ns; Loc. = LAB_X15_Y8; Fanout = 13; COMB Node = 'dds:ddsi\|AltiMult:Producti\|dataaint~204'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|q_a[6] dds:ddsi|AltiMult:Producti|dataaint~204 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1622 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(2.663 ns) 7.660 ns dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_lm01:auto_generated\|mac_mult1~DATAOUT10 4 COMB DSPMULT_X16_Y8_N0 1 " "Info: 4: + IC(0.440 ns) + CELL(2.663 ns) = 7.660 ns; Loc. = DSPMULT_X16_Y8_N0; Fanout = 1; COMB Node = 'dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_lm01:auto_generated\|mac_mult1~DATAOUT10'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.103 ns" { dds:ddsi|AltiMult:Producti|dataaint~204 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|mac_mult1~DATAOUT10 } "NODE_NAME" } } { "db/mult_lm01.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/mult_lm01.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.224 ns) 7.884 ns dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_lm01:auto_generated\|result\[10\] 5 COMB DSPOUT_X16_Y8_N2 1 " "Info: 5: + IC(0.000 ns) + CELL(0.224 ns) = 7.884 ns; Loc. = DSPOUT_X16_Y8_N2; Fanout = 1; COMB Node = 'dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_lm01:auto_generated\|result\[10\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.224 ns" { dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|mac_mult1~DATAOUT10 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|result[10] } "NODE_NAME" } } { "db/mult_lm01.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/mult_lm01.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.084 ns) 8.798 ns dds:ddsi\|AltiMult:Producti\|resdtb\[10\] 6 REG LAB_X15_Y7 1 " "Info: 6: + IC(0.830 ns) + CELL(0.084 ns) = 8.798 ns; Loc. = LAB_X15_Y7; Fanout = 1; REG Node = 'dds:ddsi\|AltiMult:Producti\|resdtb\[10\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.914 ns" { dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|result[10] dds:ddsi|AltiMult:Producti|resdtb[10] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.384 ns ( 72.56 % ) " "Info: Total cell delay = 6.384 ns ( 72.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.414 ns ( 27.44 % ) " "Info: Total interconnect delay = 2.414 ns ( 27.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.798 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|q_a[6] dds:ddsi|AltiMult:Producti|dataaint~204 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|mac_mult1~DATAOUT10 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|result[10] dds:ddsi|AltiMult:Producti|resdtb[10] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 2 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X14_Y0 X28_Y14 " "Info: The peak interconnect region extends from location X14_Y0 to location X28_Y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "10 " "Warning: Found 10 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[0\] 0 " "Info: Pin \"data_out\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[1\] 0 " "Info: Pin \"data_out\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[2\] 0 " "Info: Pin \"data_out\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[3\] 0 " "Info: Pin \"data_out\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[4\] 0 " "Info: Pin \"data_out\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[5\] 0 " "Info: Pin \"data_out\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[6\] 0 " "Info: Pin \"data_out\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[7\] 0 " "Info: Pin \"data_out\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[8\] 0 " "Info: Pin \"data_out\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[9\] 0 " "Info: Pin \"data_out\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}