ask.fnsim.qmsg

在quartus开发环境下

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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_g4e.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_g4e.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_g4e " "Info: Found entity 1: mux_g4e" {  } { { "db/mux_g4e.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/mux_g4e.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_g4e sMuxAltr:nto1Multiplexeri\|LPM_MUX:\\gc:U0\|mux_g4e:auto_generated " "Info: Elaborating entity \"mux_g4e\" for hierarchy \"sMuxAltr:nto1Multiplexeri\|LPM_MUX:\\gc:U0\|mux_g4e:auto_generated\"" {  } { { "LPM_MUX.tdf" "auto_generated" { Text "e:/altera/70/quartus/libraries/megafunctions/LPM_MUX.tdf" 86 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dds dds:ddsi " "Info: Elaborating entity \"dds\" for hierarchy \"dds:ddsi\"" {  } { { "ASK.vhd" "ddsi" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 122 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\" DSP Builder - Quartus II development tool and MATLAB/Simulink Interface - Version 6.0\" dds.vhd(64) " "Info (10544): VHDL Assertion Statement information at dds.vhd(64): assertion \"\" DSP Builder - Quartus II development tool and MATLAB/Simulink Interface - Version 6.0\"\" is always false" {  } { { "dds.vhd" "" { Text "D:/my_eda3/ASK_FSK/dds.vhd" 64 0 0 } }  } 0 10544 "VHDL Assertion Statement information at %2!s!: assertion \"%1!s!\" is always false" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SBF dds:ddsi\|SBF:AltBusi " "Info: Elaborating entity \"SBF\" for hierarchy \"dds:ddsi\|SBF:AltBusi\"" {  } { { "dds.vhd" "AltBusi" { Text "D:/my_eda3/ASK_FSK/dds.vhd" 89 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sAltrPropagate dds:ddsi\|SBF:AltBusi\|sAltrPropagate:u0 " "Info: Elaborating entity \"sAltrPropagate\" for hierarchy \"dds:ddsi\|SBF:AltBusi\|sAltrPropagate:u0\"" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "u0" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 932 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SDelay dds:ddsi\|SDelay:Delayi " "Info: Elaborating entity \"SDelay\" for hierarchy \"dds:ddsi\|SDelay:Delayi\"" {  } { { "dds.vhd" "Delayi" { Text "D:/my_eda3/ASK_FSK/dds.vhd" 103 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sAltrPropagate dds:ddsi\|SDelay:Delayi\|sAltrPropagate:u0 " "Info: Elaborating entity \"sAltrPropagate\" for hierarchy \"dds:ddsi\|SDelay:Delayi\|sAltrPropagate:u0\"" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "u0" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1297 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AltiMult dds:ddsi\|AltiMult:Producti " "Info: Elaborating entity \"AltiMult\" for hierarchy \"dds:ddsi\|AltiMult:Producti\"" {  } { { "dds.vhd" "Producti" { Text "D:/my_eda3/ASK_FSK/dds.vhd" 116 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SAdderSub dds:ddsi\|SAdderSub:ParallelAdderSubtractori " "Info: Elaborating entity \"SAdderSub\" for hierarchy \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\"" {  } { { "dds.vhd" "ParallelAdderSubtractori" { Text "D:/my_eda3/ASK_FSK/dds.vhd" 137 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/70/quartus/libraries/megafunctions/LPM_ADD_SUB.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/LPM_ADD_SUB.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "LPM_ADD_SUB.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/LPM_ADD_SUB.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}