yuanlitu.hier_info

在quartus开发环境下

|yuanlitu
pwm <= BIO_POLOR1:137.pwm
global_clk => FENPINPWM20M_10K:75.clk
global_clk => FENPINADC0809:130.clk
global_clk => AD1674CTRL:142.clk
global_clk => AD1674CTRL:143.clk
eoc => ADC0809CTRL:117.eoc
d[0] => ADC0809CTRL:117.D[0]
d[1] => ADC0809CTRL:117.D[1]
d[2] => ADC0809CTRL:117.D[2]
d[3] => ADC0809CTRL:117.D[3]
d[4] => ADC0809CTRL:117.D[4]
d[5] => ADC0809CTRL:117.D[5]
d[6] => ADC0809CTRL:117.D[6]
d[7] => ADC0809CTRL:117.D[7]
ad1674status => AD1674CTRL:142.status
ad1674[0] => AD1674CTRL:142.D[0]
ad1674[1] => AD1674CTRL:142.D[1]
ad1674[2] => AD1674CTRL:142.D[2]
ad1674[3] => AD1674CTRL:142.D[3]
ad1674[4] => AD1674CTRL:142.D[4]
ad1674[5] => AD1674CTRL:142.D[5]
ad1674[6] => AD1674CTRL:142.D[6]
ad1674[7] => AD1674CTRL:142.D[7]
ad1674[8] => AD1674CTRL:142.D[8]
ad1674[9] => AD1674CTRL:142.D[9]
ad1674[10] => AD1674CTRL:142.D[10]
ad1674[11] => AD1674CTRL:142.D[11]
ad1674statusx => AD1674CTRL:143.status
ad1674x[0] => AD1674CTRL:143.D[0]
ad1674x[1] => AD1674CTRL:143.D[1]
ad1674x[2] => AD1674CTRL:143.D[2]
ad1674x[3] => AD1674CTRL:143.D[3]
ad1674x[4] => AD1674CTRL:143.D[4]
ad1674x[5] => AD1674CTRL:143.D[5]
ad1674x[6] => AD1674CTRL:143.D[6]
ad1674x[7] => AD1674CTRL:143.D[7]
ad1674x[8] => AD1674CTRL:143.D[8]
ad1674x[9] => AD1674CTRL:143.D[9]
ad1674x[10] => AD1674CTRL:143.D[10]
ad1674x[11] => AD1674CTRL:143.D[11]
EN <= OVERCUR_CTRL:139.en
0809clk <= FENPINADC0809:130.fout
ale <= ADC0809CTRL:117.ale
start <= ADC0809CTRL:117.start
oe <= ADC0809CTRL:117.oe
1674_CSx <= AD1674CTRL:143.cs
1674_A0x <= AD1674CTRL:143.a0
1674_K12/8x <= AD1674CTRL:143.k12x8
1674_RCx <= AD1674CTRL:143.rc
1674_CS <= AD1674CTRL:142.cs
1674_A0 <= AD1674CTRL:142.a0
1674_RC <= AD1674CTRL:142.rc
1674_K12/8 <= AD1674CTRL:142.k12x8


|yuanlitu|BIO_POLOR1:137
ctrl[0] => LessThan0.IN8
ctrl[1] => LessThan0.IN7
ctrl[2] => LessThan0.IN6
ctrl[3] => LessThan0.IN5
ctrl[4] => LessThan0.IN4
ctrl[5] => LessThan0.IN3
ctrl[6] => LessThan0.IN2
ctrl[7] => LessThan0.IN1
clk => pwm~reg0.CLK
clk => cnt[0].CLK
clk => cnt[1].CLK
clk => cnt[2].CLK
clk => cnt[3].CLK
clk => cnt[4].CLK
clk => cnt[5].CLK
clk => cnt[6].CLK
clk => cnt[7].CLK
pwm <= pwm~reg0.DB_MAX_OUTPUT_PORT_TYPE


|yuanlitu|FENPINPWM20M_10K:75
clk => fout1.CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
clk => count[5].CLK
clk => count[6].CLK
clk => count[7].CLK
clk => count[8].CLK
clk => count[9].CLK
fout <= fout1.DB_MAX_OUTPUT_PORT_TYPE


|yuanlitu|OVERCUR_CTRL:139
c0809in[0] => LessThan0.IN16
c0809in[0] => LessThan1.IN16
c0809in[1] => LessThan0.IN15
c0809in[1] => LessThan1.IN15
c0809in[2] => LessThan0.IN14
c0809in[2] => LessThan1.IN14
c0809in[3] => LessThan0.IN13
c0809in[3] => LessThan1.IN13
c0809in[4] => LessThan0.IN12
c0809in[4] => LessThan1.IN12
c0809in[5] => LessThan0.IN11
c0809in[5] => LessThan1.IN11
c0809in[6] => LessThan0.IN10
c0809in[6] => LessThan1.IN10
c0809in[7] => LessThan0.IN9
c0809in[7] => LessThan1.IN9
posin[0] => Add0.IN16
posin[0] => ctrl_out~7.DATAB
posin[1] => Add0.IN15
posin[1] => ctrl_out~6.DATAB
posin[2] => Add0.IN14
posin[2] => ctrl_out~5.DATAB
posin[3] => Add0.IN13
posin[3] => ctrl_out~4.DATAB
posin[4] => Add0.IN12
posin[4] => ctrl_out~3.DATAB
posin[5] => Add0.IN11
posin[5] => ctrl_out~2.DATAB
posin[6] => Add0.IN10
posin[6] => ctrl_out~1.DATAB
posin[7] => Add0.IN9
posin[7] => ctrl_out~0.DATAB
en <= <VCC>
ctrl_out[0] <= ctrl_out~7.DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[1] <= ctrl_out~6.DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[2] <= ctrl_out~5.DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[3] <= ctrl_out~4.DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[4] <= ctrl_out~3.DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[5] <= ctrl_out~2.DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[6] <= ctrl_out~1.DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[7] <= ctrl_out~0.DB_MAX_OUTPUT_PORT_TYPE


|yuanlitu|ADC0809CTRL:117
D[0] => regl[0].DATAIN
D[1] => regl[1].DATAIN
D[2] => regl[2].DATAIN
D[3] => regl[3].DATAIN
D[4] => regl[4].DATAIN
D[5] => regl[5].DATAIN
D[6] => regl[6].DATAIN
D[7] => regl[7].DATAIN
clk => current_state~0.IN1
eoc => Selector0.IN3
eoc => next_state.st5.DATAB
eoc => Selector1.IN1
ale <= current_state.st1.DB_MAX_OUTPUT_PORT_TYPE
start <= current_state.st2.DB_MAX_OUTPUT_PORT_TYPE
oe <= oe~0.DB_MAX_OUTPUT_PORT_TYPE
clkn <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= regl[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= regl[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= regl[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= regl[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= regl[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= regl[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= regl[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= regl[7].DB_MAX_OUTPUT_PORT_TYPE


|yuanlitu|FENPINADC0809:130
clk => fout1.CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
fout <= fout1.DB_MAX_OUTPUT_PORT_TYPE


|yuanlitu|ADD_QF:116
qk[0] => LessThan1.IN10
qk[0] => Add1.IN10
qk[0] => Add0.IN10
qk[1] => LessThan1.IN9
qk[1] => Add1.IN9
qk[1] => Add0.IN9
qk[2] => LessThan1.IN8
qk[2] => Add1.IN8
qk[2] => Add0.IN8
qk[3] => LessThan1.IN7
qk[3] => Add1.IN7
qk[3] => Add0.IN7
qk[4] => LessThan1.IN6
qk[4] => Add1.IN6
qk[4] => Add0.IN6
qk[5] => LessThan1.IN5
qk[5] => Add1.IN5
qk[5] => Add0.IN5
qk[6] => LessThan1.IN4
qk[6] => Add1.IN4
qk[6] => Add0.IN4
qk[7] => LessThan1.IN3
qk[7] => Add1.IN3
qk[7] => Add0.IN3
fk[0] => LessThan0.IN18
fk[0] => LessThan1.IN18
fk[0] => Add0.IN18
fk[0] => Add1.IN18
fk[1] => LessThan0.IN17
fk[1] => LessThan1.IN17
fk[1] => Add0.IN17
fk[1] => Add1.IN17
fk[2] => LessThan0.IN16
fk[2] => LessThan1.IN16
fk[2] => Add0.IN16
fk[2] => Add1.IN16
fk[3] => LessThan0.IN15
fk[3] => LessThan1.IN15
fk[3] => Add0.IN15
fk[3] => Add1.IN15
fk[4] => LessThan0.IN14
fk[4] => LessThan1.IN14
fk[4] => Add0.IN14
fk[4] => Add1.IN14
fk[5] => LessThan0.IN13
fk[5] => LessThan1.IN13
fk[5] => Add0.IN13
fk[5] => Add1.IN13
fk[6] => LessThan0.IN12
fk[6] => LessThan1.IN12
fk[6] => Add0.IN12
fk[6] => Add1.IN12
fk[7] => LessThan0.IN11
fk[7] => LessThan1.IN11
fk[7] => Add0.IN11
fk[7] => Add1.IN11
clk => ee[0].CLK
clk => ee[1].CLK
clk => ee[2].CLK
clk => ee[3].CLK
clk => ee[4].CLK
clk => ee[5].CLK
clk => ee[6].CLK
clk => ee[7].CLK
clk => ee[8].CLK
ctrl_out[0] <= ee[0].DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[1] <= ee[1].DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[2] <= ee[2].DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[3] <= ee[3].DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[4] <= ee[4].DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[5] <= ee[5].DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[6] <= ee[6].DB_MAX_OUTPUT_PORT_TYPE
ctrl_out[7] <= ee[7].DB_MAX_OUTPUT_PORT_TYPE


|yuanlitu|AD1674CTRL:142
D[0] => regl[0].DATAIN
D[1] => regl[1].DATAIN
D[2] => regl[2].DATAIN
D[3] => regl[3].DATAIN
D[4] => regl[4].DATAIN
D[5] => regl[5].DATAIN
D[6] => regl[6].DATAIN
D[7] => regl[7].DATAIN
D[8] => regl[8].DATAIN
D[9] => regl[9].DATAIN
D[10] => regl[10].DATAIN
D[11] => regl[11].DATAIN
clk => current_state~0.IN1
status => Selector0.IN3
status => next_state.st3.DATAB
clkn <= clkn~0.DB_MAX_OUTPUT_PORT_TYPE
cs <= current_state.st0.DB_MAX_OUTPUT_PORT_TYPE
a0 <= current_state.st0.DB_MAX_OUTPUT_PORT_TYPE
rc <= rc~0.DB_MAX_OUTPUT_PORT_TYPE
k12x8 <= <VCC>
q[0] <= regl[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= regl[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= regl[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= regl[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= regl[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= regl[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= regl[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= regl[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= regl[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= regl[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= regl[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= regl[11].DB_MAX_OUTPUT_PORT_TYPE


|yuanlitu|FANKUI1:113
finput[0] => LessThan0.IN12
finput[0] => Add0.IN24
finput[0] => Add2.IN12
finput[1] => LessThan0.IN11
finput[1] => Add0.IN23
finput[1] => Add2.IN11
finput[2] => LessThan0.IN10
finput[2] => Add0.IN22
finput[2] => Add2.IN10
finput[3] => LessThan0.IN9
finput[3] => Add0.IN21
finput[3] => Add2.IN9
finput[4] => LessThan0.IN8
finput[4] => Add0.IN20
finput[4] => Add2.IN8
finput[5] => LessThan0.IN7
finput[5] => Add0.IN19
finput[5] => Add2.IN7
finput[6] => LessThan0.IN6
finput[6] => Add0.IN18
finput[6] => Add2.IN6
finput[7] => LessThan0.IN5
finput[7] => Add0.IN17
finput[7] => Add2.IN5
finput[8] => LessThan0.IN4
finput[8] => Add0.IN16
finput[8] => Add2.IN4
finput[9] => LessThan0.IN3
finput[9] => Add0.IN15
finput[9] => Add2.IN3
finput[10] => LessThan0.IN2
finput[10] => Add0.IN14
finput[10] => Add2.IN2
finput[11] => LessThan0.IN1
finput[11] => Add0.IN13
finput[11] => Add2.IN1
qinput[0] => LessThan0.IN24
qinput[0] => Add2.IN24
qinput[0] => Add0.IN12
qinput[1] => LessThan0.IN23
qinput[1] => Add2.IN23
qinput[1] => Add0.IN11
qinput[2] => LessThan0.IN22
qinput[2] => Add2.IN22
qinput[2] => Add0.IN10
qinput[3] => LessThan0.IN21
qinput[3] => Add2.IN21
qinput[3] => Add0.IN9
qinput[4] => LessThan0.IN20
qinput[4] => Add2.IN20
qinput[4] => Add0.IN8
qinput[5] => LessThan0.IN19
qinput[5] => Add2.IN19
qinput[5] => Add0.IN7
qinput[6] => LessThan0.IN18
qinput[6] => Add2.IN18
qinput[6] => Add0.IN6
qinput[7] => LessThan0.IN17
qinput[7] => Add2.IN17
qinput[7] => Add0.IN5
qinput[8] => LessThan0.IN16
qinput[8] => Add2.IN16
qinput[8] => Add0.IN4
qinput[9] => LessThan0.IN15
qinput[9] => Add2.IN15
qinput[9] => Add0.IN3
qinput[10] => LessThan0.IN14
qinput[10] => Add2.IN14
qinput[10] => Add0.IN2
qinput[11] => LessThan0.IN13
qinput[11] => Add2.IN13
qinput[11] => Add0.IN1
clk => reg2[0].CLK
clk => reg2[1].CLK
clk => reg2[2].CLK
clk => reg2[3].CLK
clk => reg2[4].CLK
clk => reg2[5].CLK
clk => reg2[6].CLK
clk => reg2[7].CLK
clk => reg2[8].CLK
clk => reg2[9].CLK
clk => reg2[10].CLK
clk => reg2[11].CLK
clk => cerror[0]~reg0.CLK
clk => cerror[1]~reg0.CLK
clk => cerror[2]~reg0.CLK
clk => cerror[3]~reg0.CLK
clk => cerror[4]~reg0.CLK
clk => cerror[5]~reg0.CLK
clk => cerror[6]~reg0.CLK
clk => cerror[7]~reg0.CLK
clk => reg1[0].CLK
clk => reg1[1].CLK
clk => reg1[2].CLK
clk => reg1[3].CLK
clk => reg1[4].CLK
clk => reg1[5].CLK
clk => reg1[6].CLK
clk => reg1[7].CLK
clk => reg1[8].CLK
clk => reg1[9].CLK
clk => reg1[10].CLK
clk => reg1[11].CLK
cerror[0] <= cerror[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cerror[1] <= cerror[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cerror[2] <= cerror[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cerror[3] <= cerror[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cerror[4] <= cerror[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cerror[5] <= cerror[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cerror[6] <= cerror[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cerror[7] <= cerror[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|yuanlitu|AD1674CTRL:143
D[0] => regl[0].DATAIN
D[1] => regl[1].DATAIN
D[2] => regl[2].DATAIN
D[3] => regl[3].DATAIN
D[4] => regl[4].DATAIN
D[5] => regl[5].DATAIN
D[6] => regl[6].DATAIN
D[7] => regl[7].DATAIN
D[8] => regl[8].DATAIN
D[9] => regl[9].DATAIN
D[10] => regl[10].DATAIN
D[11] => regl[11].DATAIN
clk => current_state~0.IN1
status => Selector0.IN3
status => next_state.st3.DATAB
clkn <= clkn~0.DB_MAX_OUTPUT_PORT_TYPE
cs <= current_state.st0.DB_MAX_OUTPUT_PORT_TYPE
a0 <= current_state.st0.DB_MAX_OUTPUT_PORT_TYPE
rc <= rc~0.DB_MAX_OUTPUT_PORT_TYPE
k12x8 <= <VCC>
q[0] <= regl[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= regl[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= regl[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= regl[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= regl[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= regl[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= regl[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= regl[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= regl[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= regl[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= regl[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= regl[11].DB_MAX_OUTPUT_PORT_TYPE


|yuanlitu|QIANKUI:114
input[0] => Add0.IN24
input[0] => reg1[0].DATAIN
input[1] => Add0.IN23
input[1] => reg1[1].DATAIN
input[2] => Add0.IN22
input[2] => reg1[2].DATAIN
input[3] => Add0.IN21
input[3] => reg1[3].DATAIN
input[4] => Add0.IN20
input[4] => reg1[4].DATAIN
input[5] => Add0.IN19
input[5] => reg1[5].DATAIN
input[6] => Add0.IN18
input[6] => reg1[6].DATAIN
input[7] => Add0.IN17
input[7] => reg1[7].DATAIN
input[8] => Add0.IN16
input[8] => reg1[8].DATAIN
input[9] => Add0.IN15
input[9] => reg1[9].DATAIN
input[10] => Add0.IN14
input[10] => reg1[10].DATAIN
input[11] => Add0.IN13
input[11] => reg1[11].DATAIN
clk => reg3[0].CLK
clk => reg3[1].CLK
clk => reg3[2].CLK
clk => reg3[3].CLK
clk => reg3[4].CLK
clk => reg3[5].CLK
clk => reg3[6].CLK
clk => reg3[7].CLK
clk => reg2[0].CLK
clk => reg2[1].CLK
clk => reg2[2].CLK
clk => reg2[3].CLK
clk => reg2[4].CLK
clk => reg2[5].CLK
clk => reg2[6].CLK
clk => reg2[7].CLK
clk => reg2[8].CLK
clk => reg2[9].CLK
clk => reg2[10].CLK
clk => reg2[11].CLK
clk => reg1[0].CLK
clk => reg1[1].CLK
clk => reg1[2].CLK
clk => reg1[3].CLK
clk => reg1[4].CLK
clk => reg1[5].CLK
clk => reg1[6].CLK
clk => reg1[7].CLK
clk => reg1[8].CLK
clk => reg1[9].CLK
clk => reg1[10].CLK
clk => reg1[11].CLK
output[0] <= reg3[0].DB_MAX_OUTPUT_PORT_TYPE
output[1] <= reg3[1].DB_MAX_OUTPUT_PORT_TYPE
output[2] <= reg3[2].DB_MAX_OUTPUT_PORT_TYPE
output[3] <= reg3[3].DB_MAX_OUTPUT_PORT_TYPE
output[4] <= reg3[4].DB_MAX_OUTPUT_PORT_TYPE
output[5] <= reg3[5].DB_MAX_OUTPUT_PORT_TYPE
output[6] <= reg3[6].DB_MAX_OUTPUT_PORT_TYPE
output[7] <= reg3[7].DB_MAX_OUTPUT_PORT_TYPE