yuanlitu.map.qmsg

在quartus开发环境下

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 26 11:12:55 2007 " "Info: Processing started: Sat May 26 11:12:55 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off yuanlitu -c yuanlitu " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off yuanlitu -c yuanlitu" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/my_eda4/fpga_program1/yuanlitu.gdf " "Warning: Can't analyze file -- file D:/my_eda4/fpga_program1/yuanlitu.gdf is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yuanlitu.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file yuanlitu.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 yuanlitu " "Info: Found entity 1: yuanlitu" {  } { { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/my_eda4/fpga_program/pwm_div_10k.vhd " "Warning: Can't analyze file -- file D:/my_eda4/fpga_program/pwm_div_10k.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "yuanlitu " "Info: Elaborating entity \"yuanlitu\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "BIO_POLOR1.vhd 2 1 " "Warning: Using design file BIO_POLOR1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bio_polor1-one " "Info: Found design unit 1: bio_polor1-one" {  } { { "BIO_POLOR1.vhd" "" { Text "D:/my_eda4/fpga_program/BIO_POLOR1.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bio_polor1 " "Info: Found entity 1: bio_polor1" {  } { { "BIO_POLOR1.vhd" "" { Text "D:/my_eda4/fpga_program/BIO_POLOR1.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BIO_POLOR1 BIO_POLOR1:137 " "Info: Elaborating entity \"BIO_POLOR1\" for hierarchy \"BIO_POLOR1:137\"" {  } { { "yuanlitu.bdf" "137" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 680 1128 1280 744 "137" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "FENPINPWM20M_10K.vhd 2 1 " "Warning: Using design file FENPINPWM20M_10K.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpinpwm20M_10k-one " "Info: Found design unit 1: fenpinpwm20M_10k-one" {  } { { "FENPINPWM20M_10K.vhd" "" { Text "D:/my_eda4/fpga_program/FENPINPWM20M_10K.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpinpwm20M_10k " "Info: Found entity 1: fenpinpwm20M_10k" {  } { { "FENPINPWM20M_10K.vhd" "" { Text "D:/my_eda4/fpga_program/FENPINPWM20M_10K.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FENPINPWM20M_10K FENPINPWM20M_10K:75 " "Info: Elaborating entity \"FENPINPWM20M_10K\" for hierarchy \"FENPINPWM20M_10K:75\"" {  } { { "yuanlitu.bdf" "75" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 680 608 712 728 "75" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "OVERCUR_CTRL.vhd 2 1 " "Warning: Using design file OVERCUR_CTRL.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 overcur_ctrl-one " "Info: Found design unit 1: overcur_ctrl-one" {  } { { "OVERCUR_CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/OVERCUR_CTRL.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 overcur_ctrl " "Info: Found entity 1: overcur_ctrl" {  } { { "OVERCUR_CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/OVERCUR_CTRL.vhd" 12 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "OVERCUR_CTRL OVERCUR_CTRL:139 " "Info: Elaborating entity \"OVERCUR_CTRL\" for hierarchy \"OVERCUR_CTRL:139\"" {  } { { "yuanlitu.bdf" "139" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 816 824 1088 880 "139" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ADC0809CTRL.vhd 2 1 " "Warning: Using design file ADC0809CTRL.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adc0809ctrl-one " "Info: Found design unit 1: adc0809ctrl-one" {  } { { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 adc0809ctrl " "Info: Found entity 1: adc0809ctrl" {  } { { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADC0809CTRL ADC0809CTRL:117 " "Info: Elaborating entity \"ADC0809CTRL\" for hierarchy \"ADC0809CTRL:117\"" {  } { { "yuanlitu.bdf" "117" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 800 392 552 912 "117" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "FENPINADC0809.vhd 2 1 " "Warning: Using design file FENPINADC0809.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpinadc0809-one " "Info: Found design unit 1: fenpinadc0809-one" {  } { { "FENPINADC0809.vhd" "" { Text "D:/my_eda4/fpga_program/FENPINADC0809.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpinadc0809 " "Info: Found entity 1: fenpinadc0809" {  } { { "FENPINADC0809.vhd" "" { Text "D:/my_eda4/fpga_program/FENPINADC0809.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FENPINADC0809 FENPINADC0809:130 " "Info: Elaborating entity \"FENPINADC0809\" for hierarchy \"FENPINADC0809:130\"" {  } { { "yuanlitu.bdf" "130" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 720 408 512 768 "130" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ADD_QF.vhd 2 1 " "Warning: Using design file ADD_QF.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add_qf-one " "Info: Found design unit 1: add_qf-one" {  } { { "ADD_QF.vhd" "" { Text "D:/my_eda4/fpga_program/ADD_QF.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add_qf " "Info: Found entity 1: add_qf" {  } { { "ADD_QF.vhd" "" { Text "D:/my_eda4/fpga_program/ADD_QF.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADD_QF ADD_QF:116 " "Info: Elaborating entity \"ADD_QF\" for hierarchy \"ADD_QF:116\"" {  } { { "yuanlitu.bdf" "116" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 400 968 1192 480 "116" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "AD1674CTRL.vhd 2 1 " "Warning: Using design file AD1674CTRL.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ad1674ctrl-one " "Info: Found design unit 1: ad1674ctrl-one" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ad1674ctrl " "Info: Found entity 1: ad1674ctrl" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}