hyperthermia_top.tan.rpt

在quartus开发环境下

; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                                                   ; To                                                                                                                                    ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 7.681 ns                         ; show_set                                               ; display:inst4|two_to_ten:inst|inte_one[1]                                                                                             ; --         ; show_set ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 22.890 ns                        ; display:inst4|two_to_ten:inst|inte_one[2]              ; inte_one[6]                                                                                                                           ; clk_20M    ; --       ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 14.679 ns                        ; show_set                                               ; deci_one[6]                                                                                                                           ; --         ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 8.378 ns                         ; show_set                                               ; display:inst4|two_to_ten:inst|inte_one[1]                                                                                             ; --         ; clk_20M  ; 0            ;
; Clock Setup: 'clk_20M'       ; N/A                                      ; None          ; 24.52 MHz ( period = 40.786 ns ) ; two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[0] ; two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component|altsyncram_p971:auto_generated|ram_block1a0~porta_address_reg0 ; clk_20M    ; clk_20M  ; 0            ;
; Clock Setup: 'set'           ; N/A                                      ; None          ; 242.01 MHz ( period = 4.132 ns ) ; sepcified_temp_top:inst2|specified_temp:inst|temp[9]   ; display:inst4|two_to_ten:inst|inte_one[2]                                                                                             ; set        ; set      ; 0            ;
; Clock Hold: 'clk_20M'        ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; temperature_top:inst7|temperature:inst|t[2]            ; two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[2]                                                                                ; clk_20M    ; clk_20M  ; 231          ;
; Clock Hold: 'set'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; sepcified_temp_top:inst2|specified_temp:inst|temp[8]   ; display:inst4|two_to_ten:inst|inte_one[2]                                                                                             ; set        ; set      ; 24           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                        ;                                                                                                                                       ;            ;          ; 255          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_20M         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; set             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;