two_dimension_fuzzy.vhd

在quartus开发环境下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity two_dimension_fuzzy is
port(t_error:in std_logic_vector(9 downto 0);----温差
     flag_e:in std_logic;             -----------温差符号位
     t_rate:in std_logic_vector(9 downto 0);-----温度变化率
     flag_r:in std_logic;              ----------温度变化率符号位
     e_rt:out std_logic_vector(7 downto 0));-----E和RT的变化量
end;
architecture one of two_dimension_fuzzy is
signal t_rate_n:std_logic_vector(9 downto 0);----温度变化率的补码
signal e:std_logic_vector(3 downto 0);----------E
signal rt:std_logic_vector(3 downto 0);---------RT
begin
e_rt<=e & rt;
process(t_error,flag_e,t_rate,flag_r)
begin
  if flag_e='1' then-----error>0
     if t_error>="0001010000" then ----error≥5
         e<="1001";
     elsif (t_error>="0001000000") and (t_error<"0001010000")then ----4≤error <5
         e<="1000";
     elsif (t_error>="0000110000") and (t_error<"0001000000")then ----3≤error <4
         e<="0111";
     elsif (t_error>="0000100000") and (t_error<"0000110000")then ----2≤error <3
         e<="0110";
     elsif (t_error>="0000010000") and (t_error<"0000100000")then ----1≤error <2
         e<="0101";
     elsif (t_error>="0000001000") and (t_error<"0000010000")then ----0.5≤error<1
         e<="0100";
     elsif (t_error>="0000000100") and (t_error<"0000001000")then ----0.25≤error<0.5
         e<="0011";
     elsif (t_error>"0000000000") and (t_error<"0000000100")then ----0<error<0.25
         e<="0011";
     elsif t_error="0000000000" then ----error=0
         e<="0001";
     end if;
  else e<="0000";----error<0
  end if;
end process;
-----------------------------------------
process(t_error,flag_e,t_rate_n,t_rate,flag_r)
begin
   if flag_r='1' then----rate>0
       if (t_rate>"0000000010") and (t_rate<="0000000100") then----0.13<rate≤0.25
          rt<="0110";
       elsif (t_rate>"0000000001") and (t_rate<="0000000010") then---0.06<rate≤0.13
          rt<="0101";
       elsif (t_rate>"0000000000") and (t_rate<="0000000001") then---0<rate≤0.06
          rt<="0100";
       elsif t_rate="0000000000" then----rate=0
          rt<="0011";
       end if;
    else -----rate<0
        t_rate_n<=("1111111111" xor t_rate)+1;-----取补码
       if (t_rate_n>"0000000000") and (t_rate_n<="0000000001") then-----0.06≤rate<0
          rt<="0010";
       elsif (t_rate_n>"0000000001") and (t_rate_n<="0000000010") then-----0.13≤rate<-0.06
          rt<="0001";
       elsif (t_rate_n>"0000000010") and (t_rate_n<="0000000100") then-----0.25≤rate<-0.13
           rt<="0000";
       end if;
    end if;
end process;
end;