hyperthermia_top.fit.qmsg

在quartus开发环境下

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "36 unused 3.30 4 31 1 " "Info: Number of I/O pins in group: 36 (unused VREF, 3.30 VCCIO, 4 input, 31 output, 1 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 4 13 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  13 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 23 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 20 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 24 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.016 ns register memory " "Info: Estimated most critical path is register to memory delay of 1.016 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns two_dimension_top:inst1\|two_dimension_fuzzy:inst\|rt\[0\] 1 REG LAB_X28_Y10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X28_Y10; Fanout = 4; REG Node = 'two_dimension_top:inst1\|two_dimension_fuzzy:inst\|rt\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[0] } "NODE_NAME" } } { "two_dimension_fuzzy.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_dimension_fuzzy.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.176 ns) 1.016 ns two_dimension_top:inst1\|lpm_rom0:inst5\|altsyncram:altsyncram_component\|altsyncram_p971:auto_generated\|ram_block1a3~porta_address_reg0 2 MEM M4K_X27_Y10 1 " "Info: 2: + IC(0.840 ns) + CELL(0.176 ns) = 1.016 ns; Loc. = M4K_X27_Y10; Fanout = 1; MEM Node = 'two_dimension_top:inst1\|lpm_rom0:inst5\|altsyncram:altsyncram_component\|altsyncram_p971:auto_generated\|ram_block1a3~porta_address_reg0'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.016 ns" { two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[0] two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component|altsyncram_p971:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_p971.tdf" "" { Text "D:/my_eda4/Hyperthermia_1/db/altsyncram_p971.tdf" 103 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.176 ns ( 17.32 % ) " "Info: Total cell delay = 0.176 ns ( 17.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.840 ns ( 82.68 % ) " "Info: Total interconnect delay = 0.840 ns ( 82.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.016 ns" { two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[0] two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component|altsyncram_p971:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}