hyperthermia_top.tan.qmsg

在quartus开发环境下

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_20M register two_dimension_top:inst1\|two_dimension_fuzzy:inst\|rt\[0\] memory two_dimension_top:inst1\|lpm_rom0:inst5\|altsyncram:altsyncram_component\|altsyncram_p971:auto_generated\|ram_block1a0~porta_address_reg0 24.52 MHz 40.786 ns Internal " "Info: Clock \"clk_20M\" has Internal fmax of 24.52 MHz between source register \"two_dimension_top:inst1\|two_dimension_fuzzy:inst\|rt\[0\]\" and destination memory \"two_dimension_top:inst1\|lpm_rom0:inst5\|altsyncram:altsyncram_component\|altsyncram_p971:auto_generated\|ram_block1a0~porta_address_reg0\" (period= 40.786 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.374 ns + Longest register memory " "Info: + Longest register to memory delay is 1.374 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns two_dimension_top:inst1\|two_dimension_fuzzy:inst\|rt\[0\] 1 REG LCCOMB_X28_Y10_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X28_Y10_N8; Fanout = 1; REG Node = 'two_dimension_top:inst1\|two_dimension_fuzzy:inst\|rt\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[0] } "NODE_NAME" } } { "two_dimension_fuzzy.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_dimension_fuzzy.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.198 ns) + CELL(0.176 ns) 1.374 ns two_dimension_top:inst1\|lpm_rom0:inst5\|altsyncram:altsyncram_component\|altsyncram_p971:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X27_Y10 4 " "Info: 2: + IC(1.198 ns) + CELL(0.176 ns) = 1.374 ns; Loc. = M4K_X27_Y10; Fanout = 4; MEM Node = 'two_dimension_top:inst1\|lpm_rom0:inst5\|altsyncram:altsyncram_component\|altsyncram_p971:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.374 ns" { two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[0] two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component|altsyncram_p971:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_p971.tdf" "" { Text "D:/my_eda4/Hyperthermia_1/db/altsyncram_p971.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.176 ns ( 12.81 % ) " "Info: Total cell delay = 0.176 ns ( 12.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.198 ns ( 87.19 % ) " "Info: Total interconnect delay = 1.198 ns ( 87.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.374 ns" { two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[0] two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component|altsyncram_p971:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.374 ns" { two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[0] two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component|altsyncram_p971:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 1.198ns } { 0.000ns 0.176ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-18.973 ns - Smallest " "Info: - Smallest clock skew is -18.973 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_20M destination 5.472 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk_20M\" to destination memory is 5.472 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk_20M 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_20M'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_20M } "NODE_NAME" } } { "Hyperthermia_top.bdf" "" { Schematic "D:/my_eda4/Hyperthermia_1/Hyperthermia_top.bdf" { { 176 -736 -568 192 "clk_20M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk_20M~clkctrl 2 COMB CLKCTRL_G1 5 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G1; Fanout = 5; COMB Node = 'clk_20M~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" ""