specified_temp.vhd

在quartus开发环境下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity specified_temp is		
	port( rise:in std_logic; -----增加温度的脉冲输入  起始温度为30℃，一次增加1℃  最大温度为45℃
          down:in std_logic;-------减小温度的脉冲输入  一次减小1℃
   		  set:in std_logic;--------整数部分或小数部分选择：set=1为整数，set=10为小数
		  specified_temp:out std_logic_vector(9 downto 0)-----设定温度输出10位二进制数
		 );
end specified_temp;
architecture behav of specified_temp is
	signal num:std_logic_vector(3 downto 0);---------总的占空比
	signal num_rise:std_logic_vector(3 downto 0);----rise脉冲计数
	signal num_down:std_logic_vector(3 downto 0);----down脉冲计数
	signal temp:std_logic_vector(9 downto 0);
begin
process(rise)-----增加温度		
begin
	if (rise'event and rise='1') then 
		if (num="0000") then num_rise<=num_rise+'1';
		elsif (num="1111") then num_rise<=num_rise;		
		else num_rise<=num_rise+1;
		end if;
	end if;
end process;
-------------------减小温度
process(down)
begin
	if (down'event and down='1') then 
		if (num="0000") then num_down<=num_down;
		elsif (num="1111") then num_down<=num_down+1; 
		else num_down<=num_down+1;
		end if;
    end if;
end process;
num<=num_rise-num_down;
---------------------------
process(set, num)
begin
	if set='1' then temp(9 downto 4)<="011110"+num;
	else temp(3 downto 0)<=num;
	end if;
end process;
------------------------
specified_temp<=temp;
end behav;