cpld_qq2812.tan.qmsg

2812学习板 cpld 源代码,2812学习板的译码部分

{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "EXINT_reg\[2\]~35 " "Warning: Node \"EXINT_reg\[2\]~35\"" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "EXINT_reg\[1\]~31 " "Warning: Node \"EXINT_reg\[1\]~31\"" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "NMI2_reg~7 " "Warning: Node \"NMI2_reg~7\"" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 73 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 73 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "EXINT_reg\[0\]~27 " "Warning: Node \"EXINT_reg\[0\]~27\"" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "NMI1_reg~7 " "Warning: Node \"NMI1_reg~7\"" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 73 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 73 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "RD " "Info: Assuming node \"RD\" is an undefined clock" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 32 -1 0 } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "RD" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "WR " "Info: Assuming node \"WR\" is an undefined clock" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 32 -1 0 } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "WR" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "RD register DSP_Data_reg\[0\] register DSP_Data_reg\[0\] 85.47 MHz 11.7 ns Internal " "Info: Clock \"RD\" has Internal fmax of 85.47 MHz between source register \"DSP_Data_reg\[0\]\" and destination register \"DSP_Data_reg\[0\]\" (period= 11.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.200 ns + Longest register register " "Info: + Longest register to register delay is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DSP_Data_reg\[0\] 1 REG LC3 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 14; REG Node = 'DSP_Data_reg\[0\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { DSP_Data_reg[0] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(1.300 ns) 4.500 ns Selector7~31 2 COMB LC1 1 " "Info: 2: + IC(3.200 ns) + CELL(1.300 ns) = 4.500 ns; Loc. = LC1; Fanout = 1; COMB Node = 'Selector7~31'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { DSP_Data_reg[0] Selector7~31 } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 5.100 ns Selector7~35 3 COMB LC2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.600 ns) = 5.100 ns; Loc. = LC2; Fanout = 1; COMB Node = 'Selector7~35'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { Selector7~31 Selector7~35 } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 7.200 ns DSP_Data_reg\[0\] 4 REG LC3 14 " "Info: 4: + IC(0.000 ns) + CELL(2.100 ns) = 7.200 ns; Loc. = LC3; Fanout = 14; REG Node = 'DSP_Data_reg\[0\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { Selector7~35 DSP_Data_reg[0] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 55.56 % ) " "Info: Total cell delay = 4.000 ns ( 55.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns ( 44.44 % ) " "Info: Total interconnect delay = 3.200 ns ( 44.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { DSP_Data_reg[0] Selector7~31 Selector7~35 DSP_Data_reg[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.200 ns" { DSP_Data_reg[0] {} Selector7~31 {} Selector7~35 {} DSP_Data_reg[0] {} } { 0.000ns 3.200ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.600ns 2.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RD destination 3.200 ns + Shortest register " "Info: + Shortest clock path from clock \"RD\" to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns RD 1 CLK PIN_D8 11 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_D8; Fanout = 11; CLK Node = 'RD'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns DSP_Data_reg\[0\] 2 REG LC3 14 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC3; Fanout = 14; REG Node = 'DSP_Data_reg\[0\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { RD DSP_Data_reg[0] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { RD DSP_Data_reg[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RD source 3.200 ns - Longest register " "Info: - Longest clock path from clock \"RD\" to source register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns RD 1 CLK PIN_D8 11 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_D8; Fanout = 11; CLK Node = 'RD'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns DSP_Data_reg\[0\] 2 REG LC3 14 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC3; Fanout = 14; REG Node = 'DSP_Data_reg\[0\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { RD DSP_Data_reg[0] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { RD DSP_Data_reg[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { RD DSP_Data_reg[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { DSP_Data_reg[0] Selector7~31 Selector7~35 DSP_Data_reg[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.200 ns" { DSP_Data_reg[0] {} Selector7~31 {} Selector7~35 {} DSP_Data_reg[0] {} } { 0.000ns 3.200ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.600ns 2.100ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { RD DSP_Data_reg[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITAN_NO_REG2REG_EXIST" "WR " "Info: No valid register-to-register data paths exist for clock \"WR\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1}