cpld_qq2812.tan.summary

2812学习板 cpld 源代码,2812学习板的译码部分

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 21.500 ns
From           : EXINT[3]
To             : DSP_Data_reg[1]
From Clock     : --
To Clock       : RD
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.400 ns
From           : LCD_Data_reg[5]
To             : LCD_Data[5]
From Clock     : WR
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 17.200 ns
From           : CS1
To             : DSP_Data[5]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.900 ns
From           : DSP_Add[2]
To             : LED_reg[1]
From Clock     : --
To Clock       : WR
Failed Paths   : 0

Type           : Clock Setup: 'RD'
Slack          : N/A
Required Time  : None
Actual Time    : 85.47 MHz ( period = 11.700 ns )
From           : DSP_Data_reg[1]
To             : DSP_Data_reg[1]
From Clock     : RD
To Clock       : RD
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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