cpld_qq2812.qsf

2812学习板 cpld 源代码,2812学习板的译码部分

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		CPLD_QQ2812_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE "EPM3256AFC256-10"
set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name TOP_LEVEL_ENTITY CPLD_QQ2812
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:19:31  MARCH 29, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
set_global_assignment -name VERILOG_FILE CPLD_QQ2812.v
set_global_assignment -name CDF_FILE CPLD_QQ2812.cdf
set_global_assignment -name MISC_FILE "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.dpf"