cpld_qq2812.acf

2812学习板 cpld 源代码,2812学习板的译码部分

--
--  Copyright (C) 1988-2002 Altera Corporation
--  Any megafunction design, and related net list (encrypted or decrypted),
--  support information, device programming or simulation file, and any other
--  associated documentation or information provided by Altera or a partner
--  under Altera's Megafunction Partnership Program may be used only to
--  program PLD devices (but not masked PLD devices) from Altera.  Any other
--  use of such megafunction design, net list, support information, device
--  programming or simulation file, or any other related documentation or
--  information is prohibited for any other purpose, including, but not
--  limited to modification, reverse engineering, de-compiling, or use with
--  any other silicon devices, unless such use is explicitly licensed under
--  a separate agreement with Altera or a megafunction partner.  Title to
--  the intellectual property, including patents, copyrights, trademarks,
--  trade secrets, or maskworks, embodied in any such megafunction design,
--  net list, support information, device programming or simulation file, or
--  any other related documentation or information provided by Altera or a
--  megafunction partner, remains with Altera, the megafunction partner, or
--  their respective licensors.  No other licenses, including any licenses
--  needed under any third party's intellectual property, are provided herein.
--
CHIP cpld_qq2812
BEGIN
	|CANRX :	OUTPUT_PIN = 48;
	|CANTX :	INPUT_PIN = 49;
	|CANTX_1 :	OUTPUT_PIN = 138;
	|CANRX_1 :	INPUT_PIN = 139;
	|SLCS :	OUTPUT_PIN = 71;
	|PATEND :	OUTPUT_PIN = 72;
	|SLOE :	OUTPUT_PIN = 74;
	|TXB1 :	OUTPUT_PIN = 83;
	|TXB :	INPUT_PIN = 86;
	|RXB :	INPUT_PIN = 84;
	|EXINT3 :	INPUT_PIN = 118;
	|EXINT2 :	INPUT_PIN = 117;
	|EXINT1 :	INPUT_PIN = 116;
	|EXINT0 :	INPUT_PIN = 113;
	|NMI2 :	INPUT_PIN = 112;
	|NMI1 :	INPUT_PIN = 111;
	|NMI :	OUTPUT_PIN = 40;
	|INT1 :	OUTPUT_PIN = 39;
	|EXINT4 :	INPUT_PIN = 140;
	|OUT15 :	OUTPUT_PIN = 37;
	|OUT14 :	OUTPUT_PIN = 36;
	|OUT13 :	OUTPUT_PIN = 35;
	|OUT12 :	OUTPUT_PIN = 34;
	|OUT11 :	OUTPUT_PIN = 32;
	|OUT10 :	OUTPUT_PIN = 31;
	|OUT9 :	OUTPUT_PIN = 30;
	|OUT8 :	OUTPUT_PIN = 29;
	|OUT7 :	OUTPUT_PIN = 28;
	|OUT6 :	OUTPUT_PIN = 27;
	|OUT5 :	OUTPUT_PIN = 25;
	|OUT4 :	OUTPUT_PIN = 23;
	|OUT3 :	OUTPUT_PIN = 22;
	|OUT2 :	OUTPUT_PIN = 21;
	|OUT1 :	OUTPUT_PIN = 19;
	|OUT0 :	OUTPUT_PIN = 18;
	|IN15 :	INPUT_PIN = 91;
	|IN14 :	INPUT_PIN = 92;
	|IN13 :	INPUT_PIN = 93;
	|IN12 :	INPUT_PIN = 96;
	|IN11 :	INPUT_PIN = 97;
	|IN10 :	INPUT_PIN = 98;
	|IN9 :	INPUT_PIN = 99;
	|IN8 :	INPUT_PIN = 100;
	|IN7 :	INPUT_PIN = 101;
	|IN6 :	INPUT_PIN = 102;
	|IN5 :	INPUT_PIN = 103;
	|IN4 :	INPUT_PIN = 106;
	|IN3 :	INPUT_PIN = 107;
	|IN2 :	INPUT_PIN = 108;
	|IN1 :	INPUT_PIN = 109;
	|IN0 :	INPUT_PIN = 110;
	|SICLK :	PIN = 87;
	|SIDIN :	OUTPUT_PIN = 88;
	|ACICS :	OUTPUT_PIN = 90;
	|SPI_CS :	OUTPUT_PIN = 38;
	|DSP_Data7 :	BIDIR_PIN = 53;
	|DSP_Data2 :	BIDIR_PIN = 54;
	|FIFO_EMPTY :	INPUT_PIN = 79;
	|FIFO_FULL :	INPUT_PIN = 80;
	|FIFO_PROG :	INPUT_PIN = 81;
	|CLKOUT :	INPUT_PIN = 62;
	|IFCLK :	INPUT_PIN = 82;
	|SLWR :	OUTPUT_PIN = 56;
	|SLRD :	OUTPUT_PIN = 55;
	|PA1 :	INPUT_PIN = 75;
	|PA0 :	INPUT_PIN = 78;
	|LCD_Data7 :	OUTPUT_PIN = 137;
	|LCD_Data6 :	OUTPUT_PIN = 136;
	|LCD_Data5 :	OUTPUT_PIN = 134;
	|LCD_Data4 :	OUTPUT_PIN = 133;
	|LCD_Data3 :	OUTPUT_PIN = 132;
	|LCD_Data2 :	OUTPUT_PIN = 131;
	|LCD_Data1 :	OUTPUT_PIN = 122;
	|LCD_Data0 :	OUTPUT_PIN = 121;
	|RS :	OUTPUT_PIN = 119;
	|E :	OUTPUT_PIN = 120;
	|LED7 :	OUTPUT_PIN = 16;
	|LED6 :	OUTPUT_PIN = 15;
	|LED5 :	OUTPUT_PIN = 14;
	|LED4 :	OUTPUT_PIN = 12;
	|LED3 :	OUTPUT_PIN = 11;
	|LED2 :	OUTPUT_PIN = 10;
	|LED1 :	OUTPUT_PIN = 9;
	|LED0 :	OUTPUT_PIN = 142;
	|Key7 :	INPUT_PIN = 143;
	|Key6 :	INPUT_PIN = 1;
	|Key5 :	INPUT_PIN = 2;
	|Key3 :	INPUT_PIN = 6;
	|Key2 :	INPUT_PIN = 8;
	|Key1 :	INPUT_PIN = 7;
	|Key0 :	INPUT_PIN = 141;
	|Key4 :	INPUT_PIN = 5;
	|DSP_Data6 :	BIDIR_PIN = 61;
	|DSP_Data5 :	BIDIR_PIN = 66;
	|DSP_Data4 :	BIDIR_PIN = 60;
	|DSP_Data3 :	BIDIR_PIN = 67;
	|DSP_Data1 :	BIDIR_PIN = 68;
	|DSP_Data0 :	BIDIR_PIN = 69;
	|DSP_ :	LOCATION = ANY;
	|DSP_Add5 :	INPUT_PIN = 42;
	|DSP_Add4 :	INPUT_PIN = 41;
	|DSP_Add3 :	INPUT_PIN = 46;
	|DSP_Add2 :	INPUT_PIN = 43;
	|DSP_Add1 :	INPUT_PIN = 45;
	|DSP_Add0 :	INPUT_PIN = 44;
	|BUZZER :	OUTPUT_PIN = 47;
	|WR :	INPUT_PIN = 70;
	|RD :	INPUT_PIN = 63;
	|CS1 :	INPUT_PIN = 65;
	DEVICE = EPM3256ATC144-7;
END;

DEFAULT_DEVICES
BEGIN
	AUTO_DEVICE = EPM3512AFC256-7;
	AUTO_DEVICE = EPM3512AQC208-7;
	AUTO_DEVICE = EPM3256AQC208-7;
	AUTO_DEVICE = EPM3256ATC144-7;
	AUTO_DEVICE = EPM3128ATC144-5;
	AUTO_DEVICE = EPM3128ATC100-5;
	AUTO_DEVICE = EPM3064ATC100-4;
	AUTO_DEVICE = EPM3064ATC44-4;
	AUTO_DEVICE = EPM3064ALC44-4;
	AUTO_DEVICE = EPM3032ATC44-4;
	AUTO_DEVICE = EPM3032ALC44-4;
	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;

TIMING_POINT
BEGIN
	DEVICE_FOR_TIMING_SYNTHESIS = EPM3256ATC144-7;
	MAINTAIN_STABLE_SYNTHESIS = OFF;
	CUT_ALL_CLEAR_PRESET = ON;
	CUT_ALL_BIDIR = ON;
END;

IGNORED_ASSIGNMENTS
BEGIN
	FIT_IGNORE_TIMING = ON;
	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
	IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
	IGNORE_DEVICE_ASSIGNMENTS = OFF;
	IGNORE_LC_ASSIGNMENTS = OFF;
	IGNORE_PIN_ASSIGNMENTS = OFF;
	IGNORE_CHIP_ASSIGNMENTS = OFF;
	IGNORE_TIMING_ASSIGNMENTS = OFF;
	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
END;

GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
	MAX7000B_ENABLE_VREFB = OFF;
	MAX7000B_ENABLE_VREFA = OFF;
	MAX7000B_VCCIO_IOBANK2 = 3.3V;
	MAX7000B_VCCIO_IOBANK1 = 3.3V;
	CONFIG_EPROM_PULLUP_RESISTOR = ON;
	CONFIG_EPROM_USER_CODE = FFFFFFFF;
	FLEX_CONFIGURATION_EPROM = AUTO;
	MAX7000AE_ENABLE_JTAG = ON;
	MAX7000AE_USER_CODE = FFFFFFFF;
	FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
	FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX6000_ENABLE_JTAG = OFF;
	CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
	MULTIVOLT_IO = OFF;
	MAX7000S_ENABLE_JTAG = ON;
	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
	MAX7000S_USER_CODE = FFFF;
	CONFIG_SCHEME_10K = PASSIVE_SERIAL;
	FLEX10K_JTAG_USER_CODE = 7F;
	ENABLE_INIT_DONE_OUTPUT = OFF;
	ENABLE_CHIP_WIDE_OE = OFF;
	ENABLE_CHIP_WIDE_RESET = OFF;
	nCEO = UNRESERVED;
	CLKUSR = UNRESERVED;
	ADD17 = UNRESERVED;
	ADD16 = UNRESERVED;
	ADD15 = UNRESERVED;
	ADD14 = UNRESERVED;
	ADD13 = UNRESERVED;
	ADD0_TO_ADD12 = UNRESERVED;
	SDOUT = RESERVED_DRIVES_OUT;
	RDCLK = UNRESERVED;
	RDYnBUSY = UNRESERVED;
	nWS_nRS_nCS_CS = UNRESERVED;
	DATA1_TO_DATA7 = UNRESERVED;
	DATA0 = RESERVED_TRI_STATED;
	FLEX8000_ENABLE_JTAG = OFF;
	CONFIG_SCHEME = ACTIVE_SERIAL;
	DISABLE_TIME_OUT = OFF;
	ENABLE_DCLK_OUTPUT = OFF;
	RELEASE_CLEARS = OFF;
	AUTO_RESTART = OFF;
	USER_CLOCK = OFF;
	SECURITY_BIT = OFF;
	RESERVED_PINS_PERCENT = 0;
	RESERVED_LCELLS_PERCENT = 0;
END;

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
	AUTO_FAST_IO = ON;
	MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = ON;
	AUTO_GLOBAL_PRESET = OFF;
	AUTO_GLOBAL_CLEAR = OFF;
	AUTO_GLOBAL_CLOCK = OFF;
	DEVICE_FAMILY = MAX3000A;
	MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
	AUTO_IMPLEMENT_IN_EAB = OFF;
	AUTO_OPEN_DRAIN_PINS = ON;
	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
	AUTO_REGISTER_PACKING = OFF;
	STYLE = NORMAL;
	AUTO_GLOBAL_OE = ON;
	OPTIMIZE_FOR_SPEED = 5;
END;

COMPILER_PROCESSING_CONFIGURATION
BEGIN
	PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
	FITTER_SETTINGS = NORMAL;
	SMART_RECOMPILE = OFF;
	GENERATE_AHDL_TDO_FILE = OFF;
	RPT_FILE_USER_ASSIGNMENTS = ON;
	RPT_FILE_LCELL_INTERCONNECT = ON;
	RPT_FILE_HIERARCHY = ON;
	RPT_FILE_EQUATIONS = ON;
	LINKED_SNF_EXTRACTOR = OFF;
	OPTIMIZE_TIMING_SNF = OFF;
	TIMING_SNF_EXTRACTOR = ON;
	FUNCTIONAL_SNF_EXTRACTOR = OFF;
	DESIGN_DOCTOR_RULES = EPLD;
	DESIGN_DOCTOR = OFF;
END;

COMPILER_INTERFACES_CONFIGURATION
BEGIN
	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
	EDIF_BUS_DELIMITERS = [];
	EDIF_FLATTEN_BUS = OFF;
	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
	EDIF_OUTPUT_USE_EDC = OFF;
	EDIF_INPUT_USE_LMF2 = OFF;
	EDIF_INPUT_USE_LMF1 = OFF;
	EDIF_OUTPUT_GND = GND;
	EDIF_OUTPUT_VCC = VCC;
	EDIF_INPUT_GND = GND;
	EDIF_INPUT_VCC = VCC;
	EDIF_OUTPUT_EDC_FILE = *.edc;
	EDIF_INPUT_LMF2 = *.lmf;
	EDIF_INPUT_LMF1 = *.lmf;
	VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
	VHDL_FLATTEN_BUS = OFF;
	VERILOG_FLATTEN_BUS = OFF;
	EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
	VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	VHDL_WRITER_VERSION = VHDL93;
	VHDL_READER_VERSION = VHDL93;
	USE_ADT_PALACE_FOR_MAX = OFF;
	SYNOPSYS_MAPPING_EFFORT = MEDIUM;
	SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
	SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
	SYNOPSYS_DESIGNWARE = OFF;
	SYNOPSYS_COMPILER = DESIGN;
	USE_SYNOPSYS_SYNTHESIS = OFF;
	VHDL_NETLIST_WRITER = OFF;
	VERILOG_NETLIST_WRITER = OFF;
	XNF_GENERATE_AHDL_TDX_FILE = ON;
	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
	EDIF_OUTPUT_VERSION = 200;
	EDIF_NETLIST_WRITER = OFF;
END;

CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
	MASTER_RESET = OFF;
	EXPANDER_NETWORKS = ON;
	RACE_CONDITIONS = ON;
	DELAY_CHAINS = ON;
	ASYNCHRONOUS_INPUTS = ON;
	PRESET_CLEAR_NETWORKS = ON;
	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
	MULTI_CLOCK_NETWORKS = ON;
	MULTI_LEVEL_CLOCKS = ON;
	GATED_CLOCKS = ON;
	RIPPLE_CLOCKS = ON;
END;

SIMULATOR_CONFIGURATION
BEGIN
	BIDIR_PIN = STRONG;
	END_TIME = 0.0ns;
	START_TIME = 0.0ns;
	GLITCH_TIME = 0.0ns;
	GLITCH = OFF;
	OSCILLATION_TIME = 0.0ns;
	OSCILLATION = OFF;
	CHECK_OUTPUTS = OFF;
	SETUP_HOLD = OFF;
	USE_DEVICE = OFF;
END;

TIMING_ANALYZER_CONFIGURATION
BEGIN
	CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
	LIST_PATH_FREQUENCY = 10MHz;