📄 cpld_qq2812.rpt
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42 -> * * - | * * * * * * * * * * * - * * - * | <-- DSP_Add5
68 -> - * - | - * * - - * - - * - * - - - - - | <-- DSP_Data1
54 -> * - - | - * * - * - * - - - * - - - - - | <-- DSP_Data2
86 -> - - * | - - - - - - - - - - * - - - - - | <-- TXB
70 -> * * - | * * * * * * * * * * * * - - - * | <-- WR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'L':
Logic cells placed in LAB 'L'
+------- LC184 DSP_Data4
| +----- LC185 DSP_Data6
| | +--- LC179 SLRD
| | | +- LC181 SLWR
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'L'
LC | | | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'L':
Pin
63 -> * * * - | - - - - - - - * - - - * - - * * | <-- RD
70 -> - - - * | * * * * * * * * * * * * - - - * | <-- WR
LC253-> - - * * | - - - - - - - - - - - * - - * - | <-- SLCS
LC159-> * - - - | - - - - - - - - - - - * - - - - | <-- ~273~2
LC196-> - * - - | - - - - - - - - - - - * - - - - | <-- DSP_Data_reg6~1
LC158-> * - - - | - - - - - - - - - - - * - - - - | <-- DSP_Data_reg4~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'M':
Logic cells placed in LAB 'M'
+- LC196 DSP_Data_reg6~1
|
| Other LABs fed by signals
| that feed LAB 'M'
LC | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'M':
Pin
65 -> * | * * * * * * * * * * * - * * - * | <-- CS1
44 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
102 -> * | - - - - - - - - - - - - * - - - | <-- IN6
92 -> * | - - - - - - - - - - - - * - - - | <-- IN14
LC185-> * | - - - - - - - - - - - - * - - - | <-- DSP_Data6
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'N':
Logic cells placed in LAB 'N'
+- LC212 DSP_Data_reg2~1
|
| Other LABs fed by signals
| that feed LAB 'N'
LC | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'N':
Pin
65 -> * | * * * * * * * * * * * - * * - * | <-- CS1
44 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42 -> * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
81 -> * | - - - - - - - - - - - - - * - - | <-- FIFO_PROG
108 -> * | - - - - - - - - - - - - - * - - | <-- IN2
98 -> * | - - - - - - - - - - - - - * - - | <-- IN10
LC115-> * | - - - - - - - - - * - - - * - - | <-- DSP_Data2
LC150-> * | - - - - - - - - - * - - - * - - | <-- :184
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'O':
Logic cells placed in LAB 'O'
+- LC227 SLOE
|
| Other LABs fed by signals
| that feed LAB 'O'
LC | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'O':
Pin
63 -> * | - - - - - - - * - - - * - - * * | <-- RD
LC253-> * | - - - - - - - - - - - * - - * - | <-- SLCS
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'P':
Logic cells placed in LAB 'P'
+------------- LC246 DSP_Data0
| +----------- LC245 DSP_Data1
| | +--------- LC243 DSP_Data3
| | | +------- LC241 DSP_Data5
| | | | +----- LC256 PATEND
| | | | | +--- LC253 SLCS
| | | | | | +- LC248 DSP_Data_reg0~5
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'P'
LC | | | | | | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'P':
LC256-> - - - - * - - | - - - - - - - - - - - - - - - * | <-- PATEND
Pin
65 -> * * - - * * * | * * * * * * * * * * * - * * - * | <-- CS1
44 -> * * - - * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45 -> * * - - * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43 -> * * - - * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46 -> * * - - * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41 -> * * - - * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42 -> * * - - * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
69 -> - - - - * - - | * - * * - * - * * * - - - - - * | <-- DSP_Data0
110 -> * - - - - - - | * - - - - - - - - - - - - - - * | <-- IN0
109 -> - * - - - - - | - - - - - - - - - * - - - - - * | <-- IN1
63 -> * * * * - - * | - - - - - - - * - - - * - - * * | <-- RD
70 -> - - - - * - - | * * * * * * * * * * * * - - - * | <-- WR
LC157-> - - * - - - - | - - - - - - - - - - - - - - - * | <-- ~273~1
LC4 -> - - - * - - - | - - - - - - - - - - - - - - - * | <-- DSP_Data_reg5~1
LC156-> - - * - - - - | - - - - - - - - - - - - - - - * | <-- DSP_Data_reg3~1
LC146-> - * - - - - - | - - - - - - - - - - - - - - - * | <-- DSP_Data_reg1~1
LC154-> - * - - - - - | - - - - - - - - - - - - - - - * | <-- DSP_Data_reg1~2
LC148-> - * - - - - - | - - - - - - - - - - - - - - - * | <-- DSP_Data_reg1~3
LC145-> - * - - - - - | - - - - - - - - - - - - - - - * | <-- DSP_Data_reg1~4
LC3 -> * - - - - - - | - - - - - - - - - - - - - - - * | <-- DSP_Data_reg0~1
LC2 -> * - - - - - - | - - - - - - - - - - - - - - - * | <-- DSP_Data_reg0~2
LC13 -> * - - - - - - | - - - - - - - - - - - - - - - * | <-- DSP_Data_reg0~3
LC1 -> * - - - - - - | - - - - - - - - - - - - - - - * | <-- DSP_Data_reg0~4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** EQUATIONS **
CANRX_1 : INPUT;
CANTX : INPUT;
CLKOUT : INPUT;
CS1 : INPUT;
DSP_Add0 : INPUT;
DSP_Add1 : INPUT;
DSP_Add2 : INPUT;
DSP_Add3 : INPUT;
DSP_Add4 : INPUT;
DSP_Add5 : INPUT;
EXINT0 : INPUT;
EXINT1 : INPUT;
EXINT2 : INPUT;
EXINT3 : INPUT;
EXINT4 : INPUT;
FIFO_EMPTY : INPUT;
FIFO_FULL : INPUT;
FIFO_PROG : INPUT;
IFCLK : INPUT;
IN0 : INPUT;
IN1 : INPUT;
IN2 : INPUT;
IN3 : INPUT;
IN4 : INPUT;
IN5 : INPUT;
IN6 : INPUT;
IN7 : INPUT;
IN8 : INPUT;
IN9 : INPUT;
IN10 : INPUT;
IN11 : INPUT;
IN12 : INPUT;
IN13 : INPUT;
IN14 : INPUT;
IN15 : INPUT;
Key0 : INPUT;
Key1 : INPUT;
Key2 : INPUT;
Key3 : INPUT;
Key4 : INPUT;
Key5 : INPUT;
Key6 : INPUT;
Key7 : INPUT;
NMI1 : INPUT;
NMI2 : INPUT;
PA0 : INPUT;
PA1 : INPUT;
RD : INPUT;
RXB : INPUT;
TXB : INPUT;
WR : INPUT;
-- Node name is 'ACICS' = 'ACICS_reg'
-- Equation name is 'ACICS', location is LC147, type is output.
ACICS = DFFE( _EQ001 $ GND, WR, VCC, VCC, VCC);
_EQ001 = !CS1 & !DSP_Add0 & DSP_Add1 & DSP_Add2 & !DSP_Add3 & !DSP_Add4 &
!DSP_Add5 & DSP_Data0
# ACICS & _X001;
_X001 = EXP(!CS1 & !DSP_Add0 & DSP_Add1 & DSP_Add2 & !DSP_Add3 & !DSP_Add4 &
!DSP_Add5);
-- Node name is 'BUZZER' = 'BUZZER_reg'
-- Equation name is 'BUZZER', location is LC123, type is output.
BUZZER = DFFE( _EQ002 $ GND, WR, VCC, VCC, VCC);
_EQ002 = !CS1 & !DSP_Add0 & !DSP_Add1 & !DSP_Add2 & !DSP_Add3 & !DSP_Add4 &
!DSP_Add5 & DSP_Data0
# BUZZER & _X002;
_X002 = EXP(!CS1 & !DSP_Add0 & !DSP_Add1 & !DSP_Add2 & !DSP_Add3 & !DSP_Add4 &
!DSP_Add5);
-- Node name is 'CANRX'
-- Equation name is 'CA⌨️ 快捷键说明
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