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Logic cells placed in LAB 'F'
+------------- LC96 LED3
| +----------- LC93 LED4
| | +--------- LC91 LED5
| | | +------- LC89 LED6
| | | | +----- LC88 LED7
| | | | | +--- LC85 OUT0
| | | | | | +- LC83 OUT1
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'F'
LC | | | | | | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'F':
LC96 -> * - - - - - - | - - - - - * - - - - - - - - - - | <-- LED3
LC93 -> - * - - - - - | - - - - - * - - - - - - - - - - | <-- LED4
LC91 -> - - * - - - - | - - - - - * - - - - - - - - - - | <-- LED5
LC89 -> - - - * - - - | - - - - - * - - - - - - - - - - | <-- LED6
LC88 -> - - - - * - - | - - - - - * - - - - - - - - - - | <-- LED7
LC85 -> - - - - - * - | - - - - - * - - - - - - - - - - | <-- OUT0
LC83 -> - - - - - - * | - - - - - * - - - - - - - - - - | <-- OUT1
Pin
65 -> * * * * * * * | * * * * * * * * * * * - * * - * | <-- CS1
44 -> * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45 -> * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43 -> * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46 -> * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41 -> * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42 -> * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
69 -> - - - - - * - | * - * * - * - * * * - - - - - * | <-- DSP_Data0
68 -> - - - - - - * | - * * - - * - - * - * - - - - - | <-- DSP_Data1
67 -> * - - - - - - | - - * - * * * - - - - - - - - - | <-- DSP_Data3
60 -> - * - - - - - | - - * - * * * - - - - - - - - - | <-- DSP_Data4
66 -> - - * - - - - | - - * - * * * - - - - - - - - - | <-- DSP_Data5
61 -> - - - * - - - | - - * - * * * - - - - - - - - - | <-- DSP_Data6
53 -> - - - - * - - | - - * * * * - - - - - - - - - - | <-- DSP_Data7
6 -> * - - - - - - | - - - - - * - - - - - - - - - - | <-- Key3
5 -> - * - - - - - | - - - - - * - - - - - - - - - - | <-- Key4
2 -> - - * - - - - | - - - - - * - - - - - - - - - - | <-- Key5
1 -> - - - * - - - | - - - - - * - - - - - - - - - - | <-- Key6
143 -> - - - - * - - | - - - - - * - - - - - - - - - - | <-- Key7
70 -> * * * * * * * | * * * * * * * * * * * * - - - * | <-- WR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+--------- LC109 OUT2
| +------- LC107 OUT3
| | +----- LC105 OUT4
| | | +--- LC104 OUT5
| | | | +- LC99 OUT6
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'G'
LC | | | | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'G':
LC109-> * - - - - | - - - - - - * - - - - - - - - - | <-- OUT2
LC107-> - * - - - | - - - - - - * - - - - - - - - - | <-- OUT3
LC105-> - - * - - | - - - - - - * - - - - - - - - - | <-- OUT4
LC104-> - - - * - | - - - - - - * - - - - - - - - - | <-- OUT5
LC99 -> - - - - * | - - - - - - * - - - - - - - - - | <-- OUT6
Pin
65 -> * * * * * | * * * * * * * * * * * - * * - * | <-- CS1
44 -> * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45 -> * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43 -> * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46 -> * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41 -> * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42 -> * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
54 -> * - - - - | - * * - * - * - - - * - - - - - | <-- DSP_Data2
67 -> - * - - - | - - * - * * * - - - - - - - - - | <-- DSP_Data3
60 -> - - * - - | - - * - * * * - - - - - - - - - | <-- DSP_Data4
66 -> - - - * - | - - * - * * * - - - - - - - - - | <-- DSP_Data5
61 -> - - - - * | - - * - * * * - - - - - - - - - | <-- DSP_Data6
70 -> * * * * * | * * * * * * * * * * * * - - - * | <-- WR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------- LC123 BUZZER
| +----- LC121 CANRX
| | +--- LC115 DSP_Data2
| | | +- LC117 DSP_Data7
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'H'
LC | | | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'H':
LC123-> * - - - | - - - - - - - * - - - - - - - - | <-- BUZZER
Pin
139 -> - * - - | - - - - - - - * - - - - - - - - | <-- CANRX_1
65 -> * - - - | * * * * * * * * * * * - * * - * | <-- CS1
44 -> * - - - | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45 -> * - - - | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43 -> * - - - | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46 -> * - - - | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41 -> * - - - | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42 -> * - - - | * * * * * * * * * * * - * * - * | <-- DSP_Add5
69 -> * - - - | * - * * - * - * * * - - - - - * | <-- DSP_Data0
63 -> - - * * | - - - - - - - * - - - * - - * * | <-- RD
70 -> * - - - | * * * * * * * * * * * * - - - * | <-- WR
LC149-> - - * - | - - - - - - - * - - - - - - - - | <-- ~274~1
LC6 -> - - - * | - - - - - - - * - - - - - - - - | <-- DSP_Data_reg7~1
LC212-> - - * - | - - - - - - - * - - - - - - - - | <-- DSP_Data_reg2~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'I':
Logic cells placed in LAB 'I'
+------- LC139 E
| +----- LC141 LCD_Data0
| | +--- LC144 LCD_Data1
| | | +- LC137 RS
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'I'
LC | | | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'I':
LC139-> * - - - | - - - - - - - - * - - - - - - - | <-- E
LC141-> - * - - | - - - - - - - - * - - - - - - - | <-- LCD_Data0
LC144-> - - * - | - - - - - - - - * - - - - - - - | <-- LCD_Data1
LC137-> - - - * | - - - - - - - - * - - - - - - - | <-- RS
Pin
65 -> * * * * | * * * * * * * * * * * - * * - * | <-- CS1
44 -> * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45 -> * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43 -> * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46 -> * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41 -> * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42 -> * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
69 -> * * - * | * - * * - * - * * * - - - - - * | <-- DSP_Data0
68 -> - - * - | - * * - - * - - * - * - - - - - | <-- DSP_Data1
70 -> * * * * | * * * * * * * * * * * * - - - * | <-- WR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'J':
Logic cells placed in LAB 'J'
+--------------------------- LC147 ACICS
| +------------------------- LC155 :182
| | +----------------------- LC151 :183
| | | +--------------------- LC150 :184
| | | | +------------------- LC152 :185
| | | | | +----------------- LC157 ~273~1
| | | | | | +--------------- LC159 ~273~2
| | | | | | | +------------- LC149 ~274~1
| | | | | | | | +----------- LC158 DSP_Data_reg4~1
| | | | | | | | | +--------- LC156 DSP_Data_reg3~1
| | | | | | | | | | +------- LC146 DSP_Data_reg1~1
| | | | | | | | | | | +----- LC154 DSP_Data_reg1~2
| | | | | | | | | | | | +--- LC148 DSP_Data_reg1~3
| | | | | | | | | | | | | +- LC145 DSP_Data_reg1~4
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'J'
LC | | | | | | | | | | | | | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'J':
LC147-> * - - - - - - - - - - - - - | - - - - - - - - - * - - - - - - | <-- ACICS
LC155-> - * - - - - - - * - - - - - | - - - - - - - - - * - - - - - - | <-- :182
LC151-> - - * - - - - - - * - - - - | - - - - - - - - - * - - - - - - | <-- :183
LC150-> - - - * - - - - - - - - - - | - - - - - - - - - * - - - * - - | <-- :184
LC152-> - - - - * - - - - - - * - * | - - - - - - - - - * - - - - - - | <-- :185
Pin
65 -> * - - - - - - - * * * * * * | * * * * * * * * * * * - * * - * | <-- CS1
44 -> * - - - - * * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45 -> * - - - - * * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43 -> * - - - - * * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46 -> * - - - - * * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41 -> * - - - - * * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42 -> * - - - - * * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
69 -> * - - - - - - - - - - - - - | * - * * - * - * * * - - - - - * | <-- DSP_Data0
116 -> - - - - * - - - - - - - - - | - - - * - - - - - * - - - - - - | <-- EXINT1
117 -> - - - * - - - - - - - - - - | - - - * - - - - - * - - - - - - | <-- EXINT2
118 -> - - * - - - - - - - - - - - | - - - * - - - - - * - - - - - - | <-- EXINT3
140 -> - * - - - - - - - - - - - - | - - - * - - - - - * - - - - - - | <-- EXINT4
80 -> - - - - - - - - - - - * - * | - - - - - - - - - * - - - - - - | <-- FIFO_FULL
109 -> - - - - - - - - - - - - * - | - - - - - - - - - * - - - - - * | <-- IN1
107 -> - - - - - - - - - * - - - - | - - - - - - - - - * - - - - - - | <-- IN3
106 -> - - - - - - - - * - - - - - | - - - - - - - - - * - - - - - - | <-- IN4
99 -> - - - - - - - - - - - - * * | - - - - - - - - - * - - - - - - | <-- IN9
97 -> - - - - - - - - - * - - - - | - - - - - - - - - * - - - - - - | <-- IN11
96 -> - - - - - - - - * - - - - - | - - - - - - - - - * - - - - - - | <-- IN12
75 -> - - - - - - - - - - * * - - | - - - - - - - - - * - - - - - - | <-- PA1
70 -> * - - - - - - - - - - - - - | * * * * * * * * * * * * - - - * | <-- WR
LC245-> - - - - - - - - - - * * * * | - - - - - - - - - * - - - - - - | <-- DSP_Data1
LC115-> - - - - - - - * - - - - - - | - - - - - - - - - * - - - * - - | <-- DSP_Data2
LC243-> - - - - - * - - - * - - - - | - - - - - - - - - * - - - - - - | <-- DSP_Data3
LC184-> - - - - - - * - * - - - - - | - - - - - - - - - * - - - - - - | <-- DSP_Data4
LC59 -> - * * * * - - - - - - - - - | * - - - - - - - - * - - - - - - | <-- INT1
LC12 -> - - - - - - - - - - - * * - | * - - - - - - - - * - - - - - - | <-- :212
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'K':
Logic cells placed in LAB 'K'
+----- LC171 SICLK
| +--- LC173 SIDIN
| | +- LC165 TXB1
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'K'
LC | | | | A B C D E F G H I J K L M N O P | Logic cells that feed LAB 'K':
LC171-> * - - | - - - - - - - - - - * - - - - - | <-- SICLK
LC173-> - * - | - - - - - - - - - - * - - - - - | <-- SIDIN
Pin
65 -> * * - | * * * * * * * * * * * - * * - * | <-- CS1
44 -> * * - | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45 -> * * - | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43 -> * * - | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46 -> * * - | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41 -> * * - | * * * * * * * * * * * - * * - * | <-- DSP_Add4
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