cpld_qq2812.rpt

2812学习板 cpld 源代码,2812学习板的译码部分

Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:               e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                             Logic cells placed in LAB 'A'
        +------------------- LC11 LED0
        | +----------------- LC10 :186
        | | +--------------- LC12 :212
        | | | +------------- LC9 :216
        | | | | +----------- LC6 DSP_Data_reg7~1
        | | | | | +--------- LC4 DSP_Data_reg5~1
        | | | | | | +------- LC3 DSP_Data_reg0~1
        | | | | | | | +----- LC2 DSP_Data_reg0~2
        | | | | | | | | +--- LC13 DSP_Data_reg0~3
        | | | | | | | | | +- LC1 DSP_Data_reg0~4
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | | | A B C D E F G H I J K L M N O P |     Logic cells that feed LAB 'A':
LC11 -> * - - - - - - - - - | * - - - - - - - - - - - - - - - | <-- LED0
LC10 -> - * - - - - - * - * | * - - - - - - - - - - - - - - - | <-- :186
LC12 -> - - * - - - - - - - | * - - - - - - - - * - - - - - - | <-- :212
LC9  -> - - - * - - - * * - | * - - - - - - - - - - - - - - - | <-- :216

Pin
65   -> * - - - * * * * * * | * * * * * * * * * * * - * * - * | <-- CS1
44   -> * - - - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45   -> * - - - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43   -> * - - - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46   -> * - - - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41   -> * - - - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42   -> * - - - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
69   -> * - - - - - - - - - | * - * * - * - * * * - - - - - * | <-- DSP_Data0
113  -> - * - - - - - - - - | * - - * - - - - - - - - - - - - | <-- EXINT0
79   -> - - - - - - - * - * | * - - - - - - - - - - - - - - - | <-- FIFO_EMPTY
110  -> - - - - - - - - * - | * - - - - - - - - - - - - - - * | <-- IN0
103  -> - - - - - * - - - - | * - - - - - - - - - - - - - - - | <-- IN5
101  -> - - - - * - - - - - | * - - - - - - - - - - - - - - - | <-- IN7
100  -> - - - - - - - - * * | * - - - - - - - - - - - - - - - | <-- IN8
93   -> - - - - - * - - - - | * - - - - - - - - - - - - - - - | <-- IN13
91   -> - - - - * - - - - - | * - - - - - - - - - - - - - - - | <-- IN15
141  -> * - - - - - - - - - | * - - - - - - - - - - - - - - - | <-- Key0
111  -> - - * * - - - - - - | * - - * - - - - - - - - - - - - | <-- NMI1
112  -> - - * * - - - - - - | * - - * - - - - - - - - - - - - | <-- NMI2
78   -> - - - - - - * * - - | * - - - - - - - - - - - - - - - | <-- PA0
70   -> * - - - - - - - - - | * * * * * * * * * * * * - - - * | <-- WR
LC246-> - - - - - - * * * * | * - - - - - - - - - - - - - - - | <-- DSP_Data0
LC241-> - - - - - * - - - - | * - - - - - - - - - - - - - - - | <-- DSP_Data5
LC117-> - - - - * - - - - - | * - - - - - - - - - - - - - - - | <-- DSP_Data7
LC59 -> - * - - - - - - - - | * - - - - - - - - * - - - - - - | <-- INT1
LC56 -> - - * * - - - - - - | * - - - - - - - - - - - - - - - | <-- NMI


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:               e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

             Logic cells placed in LAB 'B'
        +--- LC21 LED1
        | +- LC19 LED2
        | | 
        | |   Other LABs fed by signals
        | |   that feed LAB 'B'
LC      | | | A B C D E F G H I J K L M N O P |     Logic cells that feed LAB 'B':
LC21 -> * - | - * - - - - - - - - - - - - - - | <-- LED1
LC19 -> - * | - * - - - - - - - - - - - - - - | <-- LED2

Pin
65   -> * * | * * * * * * * * * * * - * * - * | <-- CS1
44   -> * * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45   -> * * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43   -> * * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46   -> * * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41   -> * * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42   -> * * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
68   -> * - | - * * - - * - - * - * - - - - - | <-- DSP_Data1
54   -> - * | - * * - * - * - - - * - - - - - | <-- DSP_Data2
7    -> * - | - * - - - - - - - - - - - - - - | <-- Key1
8    -> - * | - * - - - - - - - - - - - - - - | <-- Key2
70   -> * * | * * * * * * * * * * * * - - - * | <-- WR


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:               e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                         Logic cells placed in LAB 'C'
        +--------------- LC48 OUT7
        | +------------- LC45 OUT8
        | | +----------- LC43 OUT9
        | | | +--------- LC41 OUT10
        | | | | +------- LC40 OUT11
        | | | | | +----- LC37 OUT12
        | | | | | | +--- LC35 OUT13
        | | | | | | | +- LC33 OUT14
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | A B C D E F G H I J K L M N O P |     Logic cells that feed LAB 'C':
LC48 -> * - - - - - - - | - - * - - - - - - - - - - - - - | <-- OUT7
LC45 -> - * - - - - - - | - - * - - - - - - - - - - - - - | <-- OUT8
LC43 -> - - * - - - - - | - - * - - - - - - - - - - - - - | <-- OUT9
LC41 -> - - - * - - - - | - - * - - - - - - - - - - - - - | <-- OUT10
LC40 -> - - - - * - - - | - - * - - - - - - - - - - - - - | <-- OUT11
LC37 -> - - - - - * - - | - - * - - - - - - - - - - - - - | <-- OUT12
LC35 -> - - - - - - * - | - - * - - - - - - - - - - - - - | <-- OUT13
LC33 -> - - - - - - - * | - - * - - - - - - - - - - - - - | <-- OUT14

Pin
65   -> * * * * * * * * | * * * * * * * * * * * - * * - * | <-- CS1
44   -> * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45   -> * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43   -> * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46   -> * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41   -> * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42   -> * * * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
69   -> - * - - - - - - | * - * * - * - * * * - - - - - * | <-- DSP_Data0
68   -> - - * - - - - - | - * * - - * - - * - * - - - - - | <-- DSP_Data1
54   -> - - - * - - - - | - * * - * - * - - - * - - - - - | <-- DSP_Data2
67   -> - - - - * - - - | - - * - * * * - - - - - - - - - | <-- DSP_Data3
60   -> - - - - - * - - | - - * - * * * - - - - - - - - - | <-- DSP_Data4
66   -> - - - - - - * - | - - * - * * * - - - - - - - - - | <-- DSP_Data5
61   -> - - - - - - - * | - - * - * * * - - - - - - - - - | <-- DSP_Data6
53   -> * - - - - - - - | - - * * * * - - - - - - - - - - | <-- DSP_Data7
70   -> * * * * * * * * | * * * * * * * * * * * * - - - * | <-- WR


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:               e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                 Logic cells placed in LAB 'D'
        +------- LC59 INT1
        | +----- LC56 NMI
        | | +--- LC64 OUT15
        | | | +- LC61 SPI_CS
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'D'
LC      | | | | | A B C D E F G H I J K L M N O P |     Logic cells that feed LAB 'D':
LC64 -> - - * - | - - - * - - - - - - - - - - - - | <-- OUT15
LC61 -> - - - * | - - - * - - - - - - - - - - - - | <-- SPI_CS

Pin
65   -> - - * * | * * * * * * * * * * * - * * - * | <-- CS1
44   -> - - * * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45   -> - - * * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43   -> - - * * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46   -> - - * * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41   -> - - * * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42   -> - - * * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
69   -> - - - * | * - * * - * - * * * - - - - - * | <-- DSP_Data0
53   -> - - * - | - - * * * * - - - - - - - - - - | <-- DSP_Data7
113  -> * - - - | * - - * - - - - - - - - - - - - | <-- EXINT0
116  -> * - - - | - - - * - - - - - * - - - - - - | <-- EXINT1
117  -> * - - - | - - - * - - - - - * - - - - - - | <-- EXINT2
118  -> * - - - | - - - * - - - - - * - - - - - - | <-- EXINT3
140  -> * - - - | - - - * - - - - - * - - - - - - | <-- EXINT4
111  -> - * - - | * - - * - - - - - - - - - - - - | <-- NMI1
112  -> - * - - | * - - * - - - - - - - - - - - - | <-- NMI2
70   -> - - * * | * * * * * * * * * * * * - - - * | <-- WR


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:               e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                       Logic cells placed in LAB 'E'
        +------------- LC69 CANTX_1
        | +----------- LC80 LCD_Data2
        | | +--------- LC78 LCD_Data3
        | | | +------- LC77 LCD_Data4
        | | | | +----- LC75 LCD_Data5
        | | | | | +--- LC73 LCD_Data6
        | | | | | | +- LC72 LCD_Data7
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | A B C D E F G H I J K L M N O P |     Logic cells that feed LAB 'E':
LC80 -> - * - - - - - | - - - - * - - - - - - - - - - - | <-- LCD_Data2
LC78 -> - - * - - - - | - - - - * - - - - - - - - - - - | <-- LCD_Data3
LC77 -> - - - * - - - | - - - - * - - - - - - - - - - - | <-- LCD_Data4
LC75 -> - - - - * - - | - - - - * - - - - - - - - - - - | <-- LCD_Data5
LC73 -> - - - - - * - | - - - - * - - - - - - - - - - - | <-- LCD_Data6
LC72 -> - - - - - - * | - - - - * - - - - - - - - - - - | <-- LCD_Data7

Pin
49   -> * - - - - - - | - - - - * - - - - - - - - - - - | <-- CANTX
65   -> - * * * * * * | * * * * * * * * * * * - * * - * | <-- CS1
44   -> - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add0
45   -> - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add1
43   -> - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add2
46   -> - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add3
41   -> - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add4
42   -> - * * * * * * | * * * * * * * * * * * - * * - * | <-- DSP_Add5
54   -> - * - - - - - | - * * - * - * - - - * - - - - - | <-- DSP_Data2
67   -> - - * - - - - | - - * - * * * - - - - - - - - - | <-- DSP_Data3
60   -> - - - * - - - | - - * - * * * - - - - - - - - - | <-- DSP_Data4
66   -> - - - - * - - | - - * - * * * - - - - - - - - - | <-- DSP_Data5
61   -> - - - - - * - | - - * - * * * - - - - - - - - - | <-- DSP_Data6
53   -> - - - - - - * | - - * * * * - - - - - - - - - - | <-- DSP_Data7
70   -> - * * * * * * | * * * * * * * * * * * * - - - * | <-- WR


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:               e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':