aquisition_test.npl

CPLD初始化程序-用于DSP5416与SAA7111A的时序控制初始化

JDF G
// Created by Project Navigator ver 1.0
PROJECT aquisition_test
DESIGN aquisition_test
DEVFAM xc9500xl
DEVFAMTIME 0
DEVICE xc9572xl
DEVICETIME 0
DEVPKG PC44
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE test.vhdl
DEPASSOC acquistion acquistion.ucf
[STATUS-ALL]
acquistion.ngcFile=WARNINGS,1174896431
[STRATEGY-LIST]
Normal=True