📄 acquistion.rpt
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(unused) 0 0 0 5 FB3_11 18 I/O
(unused) 0 0 0 5 FB3_12 (b)
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 19 I/O
(unused) 0 0 0 5 FB3_15 20 I/O
(unused) 0 0 0 5 FB3_16 24 I/O
(unused) 0 0 0 5 FB3_17 22 I/O
q1 3 0 0 2 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: q1/q1_RSTF__$INT 2: tclk0 3: vcc
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q1 XXX..................................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 4/50
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 25 I/O
(unused) 0 0 0 5 FB4_3 (b)
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 26 I/O
(unused) 0 0 0 5 FB4_6 (b)
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 27 I/O
(unused) 0 0 0 5 FB4_9 (b)
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 28 I/O
(unused) 0 0 0 5 FB4_12 (b)
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 29 I/O I
outer3 1 0 0 4 FB4_15 STD 33 I/O O
tempdivclk1 1 0 0 4 FB4_16 STD (b) (b)
outer4 1 0 0 4 FB4_17 STD 34 I/O O
count<0> 0 0 0 5 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: count<0> 3: llc2 4: outer2
2: href
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
outer3 ..XX.................................... 2 2
tempdivclk1 .X...................................... 1 1
outer4 X....................................... 1 1
count<0> ........................................ 0 0
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
FTCPE_count0: FTCPE port map (count(0),'1',llc2,'0','0');
outer3 <= (llc2 AND outer2);
FTCPE_outer4: FTCPE port map (outer4,count(0),llc2,'0','0');
outer <= (q2 AND href AND tempdivclk1 AND outer4);
FDCPE_q1: FDCPE port map (q1,vcc,tclk0,NOT q1/q1_RSTF__$INT,'0');
q1/q1_RSTF__$INT <= (reset AND NOT q2);
FDCPE_q2: FDCPE port map (q2,q1,vref,NOT reset,'0');
FTCPE_tempdivclk1: FTCPE port map (tempdivclk1,'1',href,'0','0');
FTCPE_outer2: FTCPE port map (outer2,'1',llc2,'0','0');
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC9572XL-5-PC44
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
| 7 39 |
| 8 38 |
| 9 37 |
| 10 36 |
| 11 XC9572XL-5-PC44 35 |
| 12 34 |
| 13 33 |
| 14 32 |
| 15 31 |
| 16 30 |
| 17 29 |
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 vref 23 GND
2 TIE 24 TIE
3 TIE 25 TIE
4 TIE 26 TIE
5 TIE 27 TIE
6 llc2 28 TIE
7 TIE 29 tclk0
8 TIE 30 TDO
9 TIE 31 GND
10 GND 32 VCC
11 TIE 33 outer3
12 TIE 34 outer4
13 TIE 35 TIE
14 TIE 36 TIE
15 TDI 37 vcc
16 TMS 38 outer
17 TCK 39 TIE
18 TIE 40 outer2
19 TIE 41 VCC
20 TIE 42 reset
21 VCC 43 TIE
22 TIE 44 href
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572xl-5-PC44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Set Unused I/O Pin Termination : FLOAT
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
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