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📄 acquistion.rpt

📁 CPLD初始化程序-用于DSP5416与SAA7111A的时序控制初始化
💻 RPT
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cpldfit:  version G.28                              Xilinx Inc.
                                  Fitter Report
Design Name: acquistion                          Date:  3-26-2007,  4:07PM
Device Used: XC9572XL-5-PC44
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
9  /72  ( 12%) 11  /360  (  3%) 6  /72  (  8%) 10 /34  ( 29%) 15 /216 (  7%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    5           5    |  I/O              :     7       21
Output        :    4           4    |  GCK/IO           :     1        2
Bidirectional :    0           0    |  GTS/IO           :     2        0
GCK           :    1           1    |  GSR/IO           :     0        1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     10          10

MACROCELL RESOURCES:

Total Macrocells Available                    72
Registered Macrocells                          6
Non-registered Macrocell driving I/O           2

GLOBAL RESOURCES:

Signal 'llc2' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 9 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 9 macrocells used (MC).

End of Resource Summary
*************** Summary of Required Resources ******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin       Reg Init
Name                Pt      Used            Mode Rate #    Type      Use       State
count<0>            0       0       FB4_18  STD            (b)       (b)       RESET
outer               1       4       FB2_8   STD  FAST 38   I/O       O         
outer2              0       0       FB2_11  STD  FAST 40   GTS/I/O   O         RESET
outer3              1       2       FB4_15  STD  FAST 33   I/O       O         
outer4              1       1       FB4_17  STD  FAST 34   I/O       O         SET
q1                  3       3       FB3_18  STD            (b)       (b)       RESET
q1/q1_RSTF__$INT    1       2       FB1_17  STD       9    I/O       (b)       
q2                  3       3       FB1_18  STD            (b)       (b)       RESET
tempdivclk1         1       1       FB4_16  STD            (b)       (b)       RESET

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
href                                FB2_17            44   I/O       I
llc2                                FB1_11            6    GCK/I/O   GCK/I
reset                               FB2_14            42   GTS/I/O   I
tclk0                               FB4_14            29   I/O       I
vcc                                 FB2_6             37   I/O       I
vref                                FB1_2             1    I/O       I

End of Resources

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           2           4           4            4         0/0        9   
FB2           2           4           4            1         2/0        9   
FB3           1           3           3            3         0/0        9   
FB4           4           4           4            3         2/0        7   
            ----                                -----       -----     ----- 
              9                                   11         4/0       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               4/50
Number of signals used by logic mapping into function block:  4
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB1_1               (b)     
(unused)              0       0     0   5     FB1_2         1     I/O     I
(unused)              0       0     0   5     FB1_3               (b)     
(unused)              0       0     0   5     FB1_4               (b)     
(unused)              0       0     0   5     FB1_5         2     I/O     
(unused)              0       0     0   5     FB1_6         3     I/O     
(unused)              0       0     0   5     FB1_7               (b)     
(unused)              0       0     0   5     FB1_8         4     I/O     
(unused)              0       0     0   5     FB1_9         5     GCK/I/O 
(unused)              0       0     0   5     FB1_10              (b)     
(unused)              0       0     0   5     FB1_11        6     GCK/I/O GCK/I
(unused)              0       0     0   5     FB1_12              (b)     
(unused)              0       0     0   5     FB1_13              (b)     
(unused)              0       0     0   5     FB1_14        7     GCK/I/O 
(unused)              0       0     0   5     FB1_15        8     I/O     
(unused)              0       0     0   5     FB1_16              (b)     
q1/q1_RSTF__$INT      1       0     0   4     FB1_17  STD   9     I/O     (b)
q2                    3       0     0   2     FB1_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: q1                 3: reset              4: vref 
  2: q2               

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
q1/q1_RSTF__$INT     .XX..................................... 2       2
q2                   X.XX.................................... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               4/50
Number of signals used by logic mapping into function block:  4
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB2_1               (b)     
(unused)              0       0     0   5     FB2_2         35    I/O     
(unused)              0       0     0   5     FB2_3               (b)     
(unused)              0       0     0   5     FB2_4               (b)     
(unused)              0       0     0   5     FB2_5         36    I/O     
(unused)              0       0     0   5     FB2_6         37    I/O     I
(unused)              0       0     0   5     FB2_7               (b)     
outer                 1       0     0   4     FB2_8   STD   38    I/O     O
(unused)              0       0     0   5     FB2_9         39    GSR/I/O 
(unused)              0       0     0   5     FB2_10              (b)     
outer2                0       0     0   5     FB2_11  STD   40    GTS/I/O O
(unused)              0       0     0   5     FB2_12              (b)     
(unused)              0       0     0   5     FB2_13              (b)     
(unused)              0       0     0   5     FB2_14        42    GTS/I/O I
(unused)              0       0     0   5     FB2_15        43    I/O     
(unused)              0       0     0   5     FB2_16              (b)     
(unused)              0       0     0   5     FB2_17        44    I/O     I
(unused)              0       0     0   5     FB2_18              (b)     

Signals Used by Logic in Function Block
  1: href               3: q2                 4: tempdivclk1 
  2: outer4           

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
outer                XXXX.................................... 4       4
outer2               ........................................ 0       0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               3/51
Number of signals used by logic mapping into function block:  3
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB3_1               (b)     
(unused)              0       0     0   5     FB3_2         11    I/O     
(unused)              0       0     0   5     FB3_3               (b)     
(unused)              0       0     0   5     FB3_4               (b)     
(unused)              0       0     0   5     FB3_5         12    I/O     
(unused)              0       0     0   5     FB3_6               (b)     
(unused)              0       0     0   5     FB3_7               (b)     
(unused)              0       0     0   5     FB3_8         13    I/O     
(unused)              0       0     0   5     FB3_9         14    I/O     
(unused)              0       0     0   5     FB3_10              (b)     

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